| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| tR2ON |
Time from pin reset to CPU executes the first instruction |
40 | µs | ||
| tOFF2ON |
Time from wake-up from System OFF mode to CPU executes the first instruction |
34 | µs | ||
| tIDLE2CPU,POWEROFF |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction, RRAMC LOWPOWERCONFIG is using PowerOff mode. CACHE is disabled. |
17 | µs | ||
| tIDLE2CPU,CONSTLAT,POWEROFF |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction in constant latency sub-mode, RRAMC LOWPOWERCONFIG is using PowerOff mode. CACHE is disabled. |
16 | µs | ||
| tIDLE2CPU,CACHE |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction. CACHE is enabled. |
2 | µs | ||
| tIDLE2CPU,STANDBY |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction, RRAMC LOWPOWERCONFIG is using Standby mode. CACHE is disabled. |
3 | µs | ||
| tIDLE2CPU,STANDBY,STANDBY |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction, RRAMC LOWPOWERCONFIG is using Standby mode, and RRAMC STANDBYCONFIG is using Standby mode. CACHE is disabled. |
0.5 | µs | ||
| tIDLE2CPU,CACHE,CONSTLAT |
Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction in constant latency sub-mode, CACHE enabled. |
0.3 | µs |