Timing specifications


Symbol	Description	Min.	Typ.	Max.	Units
f_SPIM	Bit rates for SPIM³ ^{^b}			8	Mbps
t_SPIM,START	Time from START task to transmission started		1		µs
t_SPIM,CSCK	SCK period^{^b}	125			ns
t_SPIM,RSCK,LD	SCK rise time, standard drive^{^a}			t_RF,25pF
t_SPIM,RSCK,HD	SCK rise time, high drive^{^a}			t_HRF,25pF
t_SPIM,FSCK,LD	SCK fall time, standard drive^{^a}			t_RF,25pF
t_SPIM,FSCK,HD	SCK fall time, high drive^{^a}			t_HRF,25pF
t_SPIM,WHSCK	SCK high time^{^a}	(t_CSCK/2) - t_RSCK - 1.5 ns
t_SPIM,WLSCK	SCK low time^{^a}	(t_CSCK/2) - t_FSCK - 1.5 ns

SPI master timing diagram — Figure 6. SPIM timing diagram

³ High bit rates may require GPIOs to be set as High Drive (or Extra High Drive for devices that support it), see GPIO chapter for more details.

⁴ The achieved bit rate and SCK period follow the SPIM core clock, which depends on the selected high-frequency clock source and its accuracy. A nominal setting (for example, 8 Mbps) can therefore differ slightly from the rate on SCK without violating this specification, and the interface supports operation even in the least accurate mode. See CLOCK — Clock control for clock sources and accuracy.

⁵ At 25pF load, including GPIO pin capacitance, see GPIO spec.