The PCB layout in the following figures is the reference layout for Circuit configuration 1 for QFN48 (QFAA).
Follow these layout rules:
- Place the matching network components as close to the ANT pin of U1 as possible.
- Connect the ground of C6 only to pin 32 (VSS_PA) in the top layer.
- Connect pin 32 only to pin 49 (VSS center pad) underneath the IC package.
- Isolate the ground of C7 from all ground layers except the bottom ground layer.
- Keep the prepreg thickness between the top layer and mid layer 1 at or below 100 µm.