Two load switches are available for use as switches or LDO regulators (LDO). They have dedicated input pins where voltage cannot exceed VSYS. The input voltage can be equal to VOUT1, VOUT2, or any voltage up to the VSYS voltage.
The mode is selected using registers LDSW[n]LDOSEL.
The load switches (and LDOs) are OFF by default and can be controlled through control registers or GPIO pins using the following bits.
- Control register bits for each load switch or LDO:
- GPIO[n], once configured by host software:
When a GPIO is used to control LOADSW/LDO, it uses edges. When the GPIO toggles from LOW to HIGH, LOADSW/LDO turns ON (switch conducting). When the GPIO toggles from HIGH to LOW, LOADSW/LDO turns OFF.
Each load switch or LDO can be assigned to a separate GPIO, or a single GPIO can control both switches or LDOs.
A pull-down resistor RLSPD on the LSOUT[n] pin is enabled in a register bit for LOADSW/LDO. See register LDSW.LDSWCONFIG.
Load switch mode
Soft start is enabled by default. This ensures that the current to LSOUT[n] is limited for tSS. Once soft start is complete, there will be no current limiting provided by the load switch. Current limiting is only available from the power source connected to LSIN[n].
The soft start current limit for a load switch can be set in register LDSW.LDSWCONFIG.
LDO mode
The load switches can be independently configured as LDOs. The LDO output voltage is configurable in registers LDSW[n]VOUTSEL.
The LDO can be supplied from VOUT1, VOUT2 or VSYS, but must comply with VINLDO.