QSPI commands

nRF7002 Product Specification

nRF7002 supports several Quad Serial Peripheral Interface (QSPI) commands.

Table 1. QSPI commands
Command (byte) RDSR RDSR1 RDSR2 WRSR2 CIPHER_INIT FAST_READ READ4 PP PP4
1st byte 0x05 0x1F 0x2F 0x3F 0x4F 0x0B 0xEB 0x02 0x38
2nd byte NONCE1 AD1 ADD (6) and Dummy (2) AD1 ADD (6)
3rd byte NONCE2 AD2 Dummy (4) AD2
4th byte NONCE3 AD3 AD3
5th byte NONCE4 Dummy
Read/write Read Read Read Write Write Read Read Write Write
Action Read the values of status register 0 Read the values of status register 1 Read the values of status register 2 Write the values of status register 2 Enable the stream cipher and initialize the NONCE register Read from the selected address until SS goes high Read from the selected address until SS goes high using quad mode Write to the selected address Write to the selected address using quad mode

For read commands RDSR, RDSR1, RDSR2, FAST_READ, and READ4, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the SS can go high.

For write commands WRSR2, CIPHER_INIT, PP, and PP4, the SS must go high at the appropriate byte boundary as follows:

  • WRSR2: After 2 bytes (1 command byte, 1 payload byte) which equates to 16 clock cycles.
  • CIPHER_INIT: After 5 bytes (1 command byte, 4 payload bytes) which equates to 40 clock cycles.
  • PP: After 4+4*N bytes (1 command byte, 3 address bytes, N 32-bit words) which equates to 32 plus 32*N clock cycles.
  • PP4: After 4+4*N bytes (1 command byte, 3 address bytes, N 32-bit words) which equates to 14 plus 8*N clock cycles.

The following figures show the timing diagram for the nine supported commands.

Figure 1. RDSR (Read status register 0)
RDSR (Read status register 0)
Figure 2. RDSR1 (Read status register 1)
RDSR1 (Read status register 1)
Figure 3. RDSR2 (Read status register 2)
RDSR2 (Read status register 2)
Figure 4. WRSR2 (Write status register 2)
WRSR2 (Write status register 2)
Figure 5. CIPHER INIT (Initialize cipher)
CIPHER INIT (Initialize cipher)
Figure 6. FAST_READ
FAST_READ
Figure 7. READ4 (Quad-read input/output)
READ4 (Quad-read input/output)
Figure 8. PP (Page program)
PP (Page program)
Figure 9. PP4 (Quad-page program input/output)
PP4 (Quad-page program input/output)

There are three QSPI status registers: two are read-only, and one is both read and write. They are accessed using the QSPI commands described earlier.

RDSR0 status register

RDSR0 is a read-only register. It has a constant value read as 0x42. This register is included for compatibility with certain flash interfaces.

Table 2. Status register 0 (read only)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SRWD QE BP3 BP2 BP1 BP0 WEL WIP
Value 0 1 0 0 0 0 1 0

Additional bit field details:

  • WIP – Work in Progress
  • WEL – Write Enable Latch
  • BP0 to BP3 – Block Protect 0–3
  • QE – Quad Enable
  • SRWD – Status Register Write Disable

RDSR1 status register

RDSR1 is a read-only register. It is used to determine if an nRF70 Series device is ready for communication.

Table 3. Status register 1 (read only)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Error status Res Res Ready Awake Res
Value 0 = No error 0 0 1 = Boot complete 1 = Bus active 0

RDSR2/WRSR2 status register

RDSR2/WRSR2 is a read/write register. It is used to wake up an nRF70 Series device and prevent it from going to sleep.

Table 4. Status register 2 (read/write)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Wakeup
Value Reserved 1 = Wakeup request