SPI/QSPI timing specifications

This section provides Serial Peripheral Interface (SPI)/Quad Serial Peripheral Interface (QSPI) timing diagram and specifications.

Timing specifications for Active state, 3.3 V I/O

Table 1. Active state, 3.3 V I/O

Symbol	Description	Min.	Typ.	Max.	Units
tSPIS,CSCKIN	SCK input period	31.25			ns
tSPIS,RFSCKIN	SCK input rise/fall time			7.81	ns
tSPIS,WHSCKIN	SCK input high time	7.81			ns
tSPIS,WLSCKIN	SCK input low time	7.81			ns
tSPIS,SUCSN	CSN to CLK setup time	31.25			ns
tSPIS,HCSN	CLK to CSN hold time	31.25			ns
tSPIS,CWH	CSN inactive time	31.25			ns
tSPIS,VSO	CLK edge to MISO valid			13.10	ns
tSPIS,HSO	MISO hold time after CLK edge	3.00			ns
tSPIS,SUSI	MOSI to CLK edge setup time	2.50			ns
tSPIS,HSI	CLK edge to MOSI hold time	3.00			ns

Timing specifications for Active state, 1.8 V I/O

Table 2. Active state, 1.8 V I/O

Symbol	Description	Min.	Typ.	Max.	Units
tSPIS,CSCKIN	SCK input period	41.60			ns
tSPIS,RFSCKIN	SCK input rise/fall time			10.40	ns
tSPIS,WHSCKIN	SCK input high time	10.40			ns
tSPIS,WLSCKIN	SCK input low time	10.40			ns
tSPIS,SUCSN	CSN to CLK setup time	41.60			ns
tSPIS,HCSN	CLK to CSN hold time	41.60			ns
tSPIS,CWH	CSN inactive time	41.60			ns
tSPIS,VSO	CLK edge to MISO valid			17.50	ns
tSPIS,HSO	MISO hold time after CLK edge	3.00			ns
tSPIS,SUSI	MOSI to CLK edge setup time	2.50			ns
tSPIS,HSI	CLK edge to MOSI hold time	3.30			ns

Timing specifications for Sleep state, 1.8–3.3 V I/O

Table 3. Sleep state, 1.8–3.3 V I/O

Symbol	Description	Min.	Typ.	Max.	Units
tSPIS,CSCKIN	SCK input period	88.00			ns
tSPIS,RFSCKIN	SCK input rise/fall time			22.00	ns
tSPIS,WHSCKIN	SCK input high time	22.00			ns
tSPIS,WLSCKIN	SCK input low time	22.00			ns
tSPIS,SUCSN	CSN to CLK setup time	88.00			ns
tSPIS,HCSN	CLK to CSN hold time	88.00			ns
tSPIS,CWH	CSN inactive time	88.00			ns
tSPIS,VSO	CLK edge to MISO valid			41.50	ns
tSPIS,HSO	MISO hold time after CLK edge	3.00			ns
tSPIS,SUSI	MOSI to CLK edge setup time	2.50			ns
tSPIS,HSI	CLK edge to MOSI hold time	12.00			ns