PPI — Programmable peripheral interconnect

The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI.

The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way as ordinary PPI channels.

Table 1. Configurable and fixed PPI channels
Instance	Channel	Number of channels
PPI	0-19	20
PPI (fixed)	20-31	12

The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP, and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event.

On each PPI channel, the signals are synchronized to the 16 MHz clock to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.

Note: Shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed.

Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].

There are two ways of enabling and disabling PPI channels:

Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers.
Enable or disable PPI channels in PPI channel groups through the groups’ ENABLE and DISABLE tasks. Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI channels belong to which groups.

Note: When a channel belongs to two groups m and n, and the tasks CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), the CHG[m].EN on that channel has priority.

PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way.

Pre-programmed channels

Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application.

For a list of pre-programmed PPI channels, see the following table.

Table 2. Pre-programmed channels
Channel	EEP	TEP
20	TIMER0->EVENTS_COMPARE[0]	RADIO->TASKS_TXEN
21	TIMER0->EVENTS_COMPARE[0]	RADIO->TASKS_RXEN
22	TIMER0->EVENTS_COMPARE[1]	RADIO->TASKS_DISABLE
23	RADIO->EVENTS_BCMATCH	AAR->TASKS_START
24	RADIO->EVENTS_READY	CCM->TASKS_KSGEN
25	RADIO->EVENTS_ADDRESS	CCM->TASKS_CRYPT
26	RADIO->EVENTS_ADDRESS	TIMER0->TASKS_CAPTURE[1]
27	RADIO->EVENTS_END	TIMER0->TASKS_CAPTURE[2]
28	RTC0->EVENTS_COMPARE[0]	RADIO->TASKS_TXEN
29	RTC0->EVENTS_COMPARE[0]	RADIO->TASKS_RXEN
30	RTC0->EVENTS_COMPARE[0]	TIMER0->TASKS_CLEAR
31	RTC0->EVENTS_COMPARE[0]	TIMER0->TASKS_START

Registers

Instances


Instance	Base address	Description
PPI	0x4001F000	Programmable peripheral interconnect

Configuration


Instance	Configuration
PPI	This PPI instance has 20 configurable channels (CH[0..19]) and 12 pre-programmed channels (CH[20..31])

Register overview


Register	Offset	Description
TASKS_CHG[0].EN	0x000	Enable channel group 0
TASKS_CHG[0].DIS	0x004	Disable channel group 0
TASKS_CHG[1].EN	0x008	Enable channel group 1
TASKS_CHG[1].DIS	0x00C	Disable channel group 1
TASKS_CHG[2].EN	0x010	Enable channel group 2
TASKS_CHG[2].DIS	0x014	Disable channel group 2
TASKS_CHG[3].EN	0x018	Enable channel group 3
TASKS_CHG[3].DIS	0x01C	Disable channel group 3
TASKS_CHG[4].EN	0x020	Enable channel group 4
TASKS_CHG[4].DIS	0x024	Disable channel group 4
TASKS_CHG[5].EN	0x028	Enable channel group 5
TASKS_CHG[5].DIS	0x02C	Disable channel group 5
CHEN	0x500	Channel enable register
CHENSET	0x504	Channel enable set register
CHENCLR	0x508	Channel enable clear register
CH[0].EEP	0x510	Channel 0 event endpoint
CH[0].TEP	0x514	Channel 0 task endpoint
CH[1].EEP	0x518	Channel 1 event endpoint
CH[1].TEP	0x51C	Channel 1 task endpoint
CH[2].EEP	0x520	Channel 2 event endpoint
CH[2].TEP	0x524	Channel 2 task endpoint
CH[3].EEP	0x528	Channel 3 event endpoint
CH[3].TEP	0x52C	Channel 3 task endpoint
CH[4].EEP	0x530	Channel 4 event endpoint
CH[4].TEP	0x534	Channel 4 task endpoint
CH[5].EEP	0x538	Channel 5 event endpoint
CH[5].TEP	0x53C	Channel 5 task endpoint
CH[6].EEP	0x540	Channel 6 event endpoint
CH[6].TEP	0x544	Channel 6 task endpoint
CH[7].EEP	0x548	Channel 7 event endpoint
CH[7].TEP	0x54C	Channel 7 task endpoint
CH[8].EEP	0x550	Channel 8 event endpoint
CH[8].TEP	0x554	Channel 8 task endpoint
CH[9].EEP	0x558	Channel 9 event endpoint
CH[9].TEP	0x55C	Channel 9 task endpoint
CH[10].EEP	0x560	Channel 10 event endpoint
CH[10].TEP	0x564	Channel 10 task endpoint
CH[11].EEP	0x568	Channel 11 event endpoint
CH[11].TEP	0x56C	Channel 11 task endpoint
CH[12].EEP	0x570	Channel 12 event endpoint
CH[12].TEP	0x574	Channel 12 task endpoint
CH[13].EEP	0x578	Channel 13 event endpoint
CH[13].TEP	0x57C	Channel 13 task endpoint
CH[14].EEP	0x580	Channel 14 event endpoint
CH[14].TEP	0x584	Channel 14 task endpoint
CH[15].EEP	0x588	Channel 15 event endpoint
CH[15].TEP	0x58C	Channel 15 task endpoint
CH[16].EEP	0x590	Channel 16 event endpoint
CH[16].TEP	0x594	Channel 16 task endpoint
CH[17].EEP	0x598	Channel 17 event endpoint
CH[17].TEP	0x59C	Channel 17 task endpoint
CH[18].EEP	0x5A0	Channel 18 event endpoint
CH[18].TEP	0x5A4	Channel 18 task endpoint
CH[19].EEP	0x5A8	Channel 19 event endpoint
CH[19].TEP	0x5AC	Channel 19 task endpoint
CHG[0]	0x800	Channel group 0
CHG[1]	0x804	Channel group 1
CHG[2]	0x808	Channel group 2
CHG[3]	0x80C	Channel group 3
CHG[4]	0x810	Channel group 4
CHG[5]	0x814	Channel group 5
FORK[0].TEP	0x910	Channel 0 task endpoint
FORK[1].TEP	0x914	Channel 1 task endpoint
FORK[2].TEP	0x918	Channel 2 task endpoint
FORK[3].TEP	0x91C	Channel 3 task endpoint
FORK[4].TEP	0x920	Channel 4 task endpoint
FORK[5].TEP	0x924	Channel 5 task endpoint
FORK[6].TEP	0x928	Channel 6 task endpoint
FORK[7].TEP	0x92C	Channel 7 task endpoint
FORK[8].TEP	0x930	Channel 8 task endpoint
FORK[9].TEP	0x934	Channel 9 task endpoint
FORK[10].TEP	0x938	Channel 10 task endpoint
FORK[11].TEP	0x93C	Channel 11 task endpoint
FORK[12].TEP	0x940	Channel 12 task endpoint
FORK[13].TEP	0x944	Channel 13 task endpoint
FORK[14].TEP	0x948	Channel 14 task endpoint
FORK[15].TEP	0x94C	Channel 15 task endpoint
FORK[16].TEP	0x950	Channel 16 task endpoint
FORK[17].TEP	0x954	Channel 17 task endpoint
FORK[18].TEP	0x958	Channel 18 task endpoint
FORK[19].TEP	0x95C	Channel 19 task endpoint
FORK[20].TEP	0x960	Channel 20 task endpoint
FORK[21].TEP	0x964	Channel 21 task endpoint
FORK[22].TEP	0x968	Channel 22 task endpoint
FORK[23].TEP	0x96C	Channel 23 task endpoint
FORK[24].TEP	0x970	Channel 24 task endpoint
FORK[25].TEP	0x974	Channel 25 task endpoint
FORK[26].TEP	0x978	Channel 26 task endpoint
FORK[27].TEP	0x97C	Channel 27 task endpoint
FORK[28].TEP	0x980	Channel 28 task endpoint
FORK[29].TEP	0x984	Channel 29 task endpoint
FORK[30].TEP	0x988	Channel 30 task endpoint
FORK[31].TEP	0x98C	Channel 31 task endpoint

TASKS_CHG[0]

Channel group tasks

TASKS_CHG[0].EN

Address offset: 0x000

Enable channel group 0


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 0
			Trigger	1								Trigger task

TASKS_CHG[0].DIS

Address offset: 0x004

Disable channel group 0


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 0
			Trigger	1								Trigger task

TASKS_CHG[1]

Channel group tasks

TASKS_CHG[1].EN

Address offset: 0x008

Enable channel group 1


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 1
			Trigger	1								Trigger task

TASKS_CHG[1].DIS

Address offset: 0x00C

Disable channel group 1


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 1
			Trigger	1								Trigger task

TASKS_CHG[2]

Channel group tasks

TASKS_CHG[2].EN

Address offset: 0x010

Enable channel group 2


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 2
			Trigger	1								Trigger task

TASKS_CHG[2].DIS

Address offset: 0x014

Disable channel group 2


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 2
			Trigger	1								Trigger task

TASKS_CHG[3]

Channel group tasks

TASKS_CHG[3].EN

Address offset: 0x018

Enable channel group 3


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 3
			Trigger	1								Trigger task

TASKS_CHG[3].DIS

Address offset: 0x01C

Disable channel group 3


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 3
			Trigger	1								Trigger task

TASKS_CHG[4]

Channel group tasks

TASKS_CHG[4].EN

Address offset: 0x020

Enable channel group 4


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 4
			Trigger	1								Trigger task

TASKS_CHG[4].DIS

Address offset: 0x024

Disable channel group 4


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 4
			Trigger	1								Trigger task

TASKS_CHG[5]

Channel group tasks

TASKS_CHG[5].EN

Address offset: 0x028

Enable channel group 5


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EN										Enable channel group 5
			Trigger	1								Trigger task

TASKS_CHG[5].DIS

Address offset: 0x02C

Disable channel group 5


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIS										Disable channel group 5
			Trigger	1								Trigger task

CHEN

Address offset: 0x500

Channel enable register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Enable or disable channel 0
			Disabled	0								Disable channel
			Enabled	1								Enable channel
B	RW	CH1										Enable or disable channel 1
			Disabled	0								Disable channel
			Enabled	1								Enable channel
C	RW	CH2										Enable or disable channel 2
			Disabled	0								Disable channel
			Enabled	1								Enable channel
D	RW	CH3										Enable or disable channel 3
			Disabled	0								Disable channel
			Enabled	1								Enable channel
E	RW	CH4										Enable or disable channel 4
			Disabled	0								Disable channel
			Enabled	1								Enable channel
F	RW	CH5										Enable or disable channel 5
			Disabled	0								Disable channel
			Enabled	1								Enable channel
G	RW	CH6										Enable or disable channel 6
			Disabled	0								Disable channel
			Enabled	1								Enable channel
H	RW	CH7										Enable or disable channel 7
			Disabled	0								Disable channel
			Enabled	1								Enable channel
I	RW	CH8										Enable or disable channel 8
			Disabled	0								Disable channel
			Enabled	1								Enable channel
J	RW	CH9										Enable or disable channel 9
			Disabled	0								Disable channel
			Enabled	1								Enable channel
K	RW	CH10										Enable or disable channel 10
			Disabled	0								Disable channel
			Enabled	1								Enable channel
L	RW	CH11										Enable or disable channel 11
			Disabled	0								Disable channel
			Enabled	1								Enable channel
M	RW	CH12										Enable or disable channel 12
			Disabled	0								Disable channel
			Enabled	1								Enable channel
N	RW	CH13										Enable or disable channel 13
			Disabled	0								Disable channel
			Enabled	1								Enable channel
O	RW	CH14										Enable or disable channel 14
			Disabled	0								Disable channel
			Enabled	1								Enable channel
P	RW	CH15										Enable or disable channel 15
			Disabled	0								Disable channel
			Enabled	1								Enable channel
Q	RW	CH16										Enable or disable channel 16
			Disabled	0								Disable channel
			Enabled	1								Enable channel
R	RW	CH17										Enable or disable channel 17
			Disabled	0								Disable channel
			Enabled	1								Enable channel
S	RW	CH18										Enable or disable channel 18
			Disabled	0								Disable channel
			Enabled	1								Enable channel
T	RW	CH19										Enable or disable channel 19
			Disabled	0								Disable channel
			Enabled	1								Enable channel
U	RW	CH20										Enable or disable channel 20
			Disabled	0								Disable channel
			Enabled	1								Enable channel
V	RW	CH21										Enable or disable channel 21
			Disabled	0								Disable channel
			Enabled	1								Enable channel
W	RW	CH22										Enable or disable channel 22
			Disabled	0								Disable channel
			Enabled	1								Enable channel
X	RW	CH23										Enable or disable channel 23
			Disabled	0								Disable channel
			Enabled	1								Enable channel
Y	RW	CH24										Enable or disable channel 24
			Disabled	0								Disable channel
			Enabled	1								Enable channel
Z	RW	CH25										Enable or disable channel 25
			Disabled	0								Disable channel
			Enabled	1								Enable channel
a	RW	CH26										Enable or disable channel 26
			Disabled	0								Disable channel
			Enabled	1								Enable channel
b	RW	CH27										Enable or disable channel 27
			Disabled	0								Disable channel
			Enabled	1								Enable channel
c	RW	CH28										Enable or disable channel 28
			Disabled	0								Disable channel
			Enabled	1								Enable channel
d	RW	CH29										Enable or disable channel 29
			Disabled	0								Disable channel
			Enabled	1								Enable channel
e	RW	CH30										Enable or disable channel 30
			Disabled	0								Disable channel
			Enabled	1								Enable channel
f	RW	CH31										Enable or disable channel 31
			Disabled	0								Disable channel
			Enabled	1								Enable channel

CHENSET

Address offset: 0x504

Channel enable set register

Note: Read: reads value of CHi field in CHEN register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	CH0										Channel 0 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
B	RW W1S	CH1										Channel 1 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
C	RW W1S	CH2										Channel 2 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
D	RW W1S	CH3										Channel 3 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
E	RW W1S	CH4										Channel 4 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
F	RW W1S	CH5										Channel 5 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
G	RW W1S	CH6										Channel 6 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
H	RW W1S	CH7										Channel 7 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
I	RW W1S	CH8										Channel 8 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
J	RW W1S	CH9										Channel 9 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
K	RW W1S	CH10										Channel 10 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
L	RW W1S	CH11										Channel 11 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
M	RW W1S	CH12										Channel 12 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
N	RW W1S	CH13										Channel 13 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
O	RW W1S	CH14										Channel 14 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
P	RW W1S	CH15										Channel 15 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
Q	RW W1S	CH16										Channel 16 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
R	RW W1S	CH17										Channel 17 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
S	RW W1S	CH18										Channel 18 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
T	RW W1S	CH19										Channel 19 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
U	RW W1S	CH20										Channel 20 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
V	RW W1S	CH21										Channel 21 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
W	RW W1S	CH22										Channel 22 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
X	RW W1S	CH23										Channel 23 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
Y	RW W1S	CH24										Channel 24 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
Z	RW W1S	CH25										Channel 25 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
a	RW W1S	CH26										Channel 26 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
b	RW W1S	CH27										Channel 27 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
c	RW W1S	CH28										Channel 28 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
d	RW W1S	CH29										Channel 29 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
e	RW W1S	CH30										Channel 30 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel
f	RW W1S	CH31										Channel 31 enable set register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Set	1								Write: Enable channel

CHENCLR

Address offset: 0x508

Channel enable clear register

Note: Read: reads value of CHi field in CHEN register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	CH0										Channel 0 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
B	RW W1C	CH1										Channel 1 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
C	RW W1C	CH2										Channel 2 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
D	RW W1C	CH3										Channel 3 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
E	RW W1C	CH4										Channel 4 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
F	RW W1C	CH5										Channel 5 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
G	RW W1C	CH6										Channel 6 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
H	RW W1C	CH7										Channel 7 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
I	RW W1C	CH8										Channel 8 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
J	RW W1C	CH9										Channel 9 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
K	RW W1C	CH10										Channel 10 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
L	RW W1C	CH11										Channel 11 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
M	RW W1C	CH12										Channel 12 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
N	RW W1C	CH13										Channel 13 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
O	RW W1C	CH14										Channel 14 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
P	RW W1C	CH15										Channel 15 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
Q	RW W1C	CH16										Channel 16 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
R	RW W1C	CH17										Channel 17 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
S	RW W1C	CH18										Channel 18 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
T	RW W1C	CH19										Channel 19 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
U	RW W1C	CH20										Channel 20 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
V	RW W1C	CH21										Channel 21 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
W	RW W1C	CH22										Channel 22 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
X	RW W1C	CH23										Channel 23 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
Y	RW W1C	CH24										Channel 24 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
Z	RW W1C	CH25										Channel 25 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
a	RW W1C	CH26										Channel 26 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
b	RW W1C	CH27										Channel 27 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
c	RW W1C	CH28										Channel 28 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
d	RW W1C	CH29										Channel 29 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
e	RW W1C	CH30										Channel 30 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel
f	RW W1C	CH31										Channel 31 enable clear register. Writing '0' has no effect.
			Disabled	0								Read: channel disabled
			Enabled	1								Read: channel enabled
			Clear	1								Write: disable channel

CH[0]

PPI Channel

CH[0].EEP

Address offset: 0x510

Channel 0 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[0].TEP

Address offset: 0x514

Channel 0 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[1]

PPI Channel

CH[1].EEP

Address offset: 0x518

Channel 1 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[1].TEP

Address offset: 0x51C

Channel 1 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[2]

PPI Channel

CH[2].EEP

Address offset: 0x520

Channel 2 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[2].TEP

Address offset: 0x524

Channel 2 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[3]

PPI Channel

CH[3].EEP

Address offset: 0x528

Channel 3 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[3].TEP

Address offset: 0x52C

Channel 3 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[4]

PPI Channel

CH[4].EEP

Address offset: 0x530

Channel 4 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[4].TEP

Address offset: 0x534

Channel 4 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[5]

PPI Channel

CH[5].EEP

Address offset: 0x538

Channel 5 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[5].TEP

Address offset: 0x53C

Channel 5 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[6]

PPI Channel

CH[6].EEP

Address offset: 0x540

Channel 6 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[6].TEP

Address offset: 0x544

Channel 6 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[7]

PPI Channel

CH[7].EEP

Address offset: 0x548

Channel 7 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[7].TEP

Address offset: 0x54C

Channel 7 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[8]

PPI Channel

CH[8].EEP

Address offset: 0x550

Channel 8 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[8].TEP

Address offset: 0x554

Channel 8 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[9]

PPI Channel

CH[9].EEP

Address offset: 0x558

Channel 9 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[9].TEP

Address offset: 0x55C

Channel 9 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[10]

PPI Channel

CH[10].EEP

Address offset: 0x560

Channel 10 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[10].TEP

Address offset: 0x564

Channel 10 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[11]

PPI Channel

CH[11].EEP

Address offset: 0x568

Channel 11 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[11].TEP

Address offset: 0x56C

Channel 11 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[12]

PPI Channel

CH[12].EEP

Address offset: 0x570

Channel 12 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[12].TEP

Address offset: 0x574

Channel 12 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[13]

PPI Channel

CH[13].EEP

Address offset: 0x578

Channel 13 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[13].TEP

Address offset: 0x57C

Channel 13 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[14]

PPI Channel

CH[14].EEP

Address offset: 0x580

Channel 14 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[14].TEP

Address offset: 0x584

Channel 14 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[15]

PPI Channel

CH[15].EEP

Address offset: 0x588

Channel 15 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[15].TEP

Address offset: 0x58C

Channel 15 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[16]

PPI Channel

CH[16].EEP

Address offset: 0x590

Channel 16 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[16].TEP

Address offset: 0x594

Channel 16 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[17]

PPI Channel

CH[17].EEP

Address offset: 0x598

Channel 17 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[17].TEP

Address offset: 0x59C

Channel 17 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[18]

PPI Channel

CH[18].EEP

Address offset: 0x5A0

Channel 18 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[18].TEP

Address offset: 0x5A4

Channel 18 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CH[19]

PPI Channel

CH[19].EEP

Address offset: 0x5A8

Channel 19 event endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EEP										Pointer to event register. Accepts only addresses to registers from the Event group.

CH[19].TEP

Address offset: 0x5AC

Channel 19 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register. Accepts only addresses to registers from the Task group.

CHG[0]

Address offset: 0x800

Channel group 0


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

CHG[1]

Address offset: 0x804

Channel group 1


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

CHG[2]

Address offset: 0x808

Channel group 2


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

CHG[3]

Address offset: 0x80C

Channel group 3


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

CHG[4]

Address offset: 0x810

Channel group 4


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

CHG[5]

Address offset: 0x814

Channel group 5


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CH0										Include or exclude channel 0
			Excluded	0								Exclude
			Included	1								Include
B	RW	CH1										Include or exclude channel 1
			Excluded	0								Exclude
			Included	1								Include
C	RW	CH2										Include or exclude channel 2
			Excluded	0								Exclude
			Included	1								Include
D	RW	CH3										Include or exclude channel 3
			Excluded	0								Exclude
			Included	1								Include
E	RW	CH4										Include or exclude channel 4
			Excluded	0								Exclude
			Included	1								Include
F	RW	CH5										Include or exclude channel 5
			Excluded	0								Exclude
			Included	1								Include
G	RW	CH6										Include or exclude channel 6
			Excluded	0								Exclude
			Included	1								Include
H	RW	CH7										Include or exclude channel 7
			Excluded	0								Exclude
			Included	1								Include
I	RW	CH8										Include or exclude channel 8
			Excluded	0								Exclude
			Included	1								Include
J	RW	CH9										Include or exclude channel 9
			Excluded	0								Exclude
			Included	1								Include
K	RW	CH10										Include or exclude channel 10
			Excluded	0								Exclude
			Included	1								Include
L	RW	CH11										Include or exclude channel 11
			Excluded	0								Exclude
			Included	1								Include
M	RW	CH12										Include or exclude channel 12
			Excluded	0								Exclude
			Included	1								Include
N	RW	CH13										Include or exclude channel 13
			Excluded	0								Exclude
			Included	1								Include
O	RW	CH14										Include or exclude channel 14
			Excluded	0								Exclude
			Included	1								Include
P	RW	CH15										Include or exclude channel 15
			Excluded	0								Exclude
			Included	1								Include
Q	RW	CH16										Include or exclude channel 16
			Excluded	0								Exclude
			Included	1								Include
R	RW	CH17										Include or exclude channel 17
			Excluded	0								Exclude
			Included	1								Include
S	RW	CH18										Include or exclude channel 18
			Excluded	0								Exclude
			Included	1								Include
T	RW	CH19										Include or exclude channel 19
			Excluded	0								Exclude
			Included	1								Include
U	RW	CH20										Include or exclude channel 20
			Excluded	0								Exclude
			Included	1								Include
V	RW	CH21										Include or exclude channel 21
			Excluded	0								Exclude
			Included	1								Include
W	RW	CH22										Include or exclude channel 22
			Excluded	0								Exclude
			Included	1								Include
X	RW	CH23										Include or exclude channel 23
			Excluded	0								Exclude
			Included	1								Include
Y	RW	CH24										Include or exclude channel 24
			Excluded	0								Exclude
			Included	1								Include
Z	RW	CH25										Include or exclude channel 25
			Excluded	0								Exclude
			Included	1								Include
a	RW	CH26										Include or exclude channel 26
			Excluded	0								Exclude
			Included	1								Include
b	RW	CH27										Include or exclude channel 27
			Excluded	0								Exclude
			Included	1								Include
c	RW	CH28										Include or exclude channel 28
			Excluded	0								Exclude
			Included	1								Include
d	RW	CH29										Include or exclude channel 29
			Excluded	0								Exclude
			Included	1								Include
e	RW	CH30										Include or exclude channel 30
			Excluded	0								Exclude
			Included	1								Include
f	RW	CH31										Include or exclude channel 31
			Excluded	0								Exclude
			Included	1								Include

FORK[0]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[0].TEP

Address offset: 0x910

Channel 0 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[1]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[1].TEP

Address offset: 0x914

Channel 1 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[2]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[2].TEP

Address offset: 0x918

Channel 2 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[3]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[3].TEP

Address offset: 0x91C

Channel 3 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[4]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[4].TEP

Address offset: 0x920

Channel 4 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[5]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[5].TEP

Address offset: 0x924

Channel 5 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[6]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[6].TEP

Address offset: 0x928

Channel 6 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[7]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[7].TEP

Address offset: 0x92C

Channel 7 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[8]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[8].TEP

Address offset: 0x930

Channel 8 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[9]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[9].TEP

Address offset: 0x934

Channel 9 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[10]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[10].TEP

Address offset: 0x938

Channel 10 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[11]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[11].TEP

Address offset: 0x93C

Channel 11 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[12]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[12].TEP

Address offset: 0x940

Channel 12 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[13]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[13].TEP

Address offset: 0x944

Channel 13 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[14]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[14].TEP

Address offset: 0x948

Channel 14 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[15]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[15].TEP

Address offset: 0x94C

Channel 15 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[16]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[16].TEP

Address offset: 0x950

Channel 16 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[17]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[17].TEP

Address offset: 0x954

Channel 17 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[18]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[18].TEP

Address offset: 0x958

Channel 18 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[19]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[19].TEP

Address offset: 0x95C

Channel 19 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[20]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[20].TEP

Address offset: 0x960

Channel 20 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[21]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[21].TEP

Address offset: 0x964

Channel 21 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[22]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[22].TEP

Address offset: 0x968

Channel 22 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[23]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[23].TEP

Address offset: 0x96C

Channel 23 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[24]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[24].TEP

Address offset: 0x970

Channel 24 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[25]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[25].TEP

Address offset: 0x974

Channel 25 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[26]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[26].TEP

Address offset: 0x978

Channel 26 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[27]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[27].TEP

Address offset: 0x97C

Channel 27 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[28]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[28].TEP

Address offset: 0x980

Channel 28 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[29]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[29].TEP

Address offset: 0x984

Channel 29 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[30]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[30].TEP

Address offset: 0x988

Channel 30 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register

FORK[31]

Fork

This fork provides a second set of task endpoints for each of the channels in the PPI.

FORK[31].TEP

Address offset: 0x98C

Channel 31 task endpoint


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TEP										Pointer to task register