The pin assignment figures and tables describe the pinouts for the product variants of the chip.

The nRF52840 device provides flexibility regarding GPIO pin routing and configuration. However, some pins have limitations or recommendations for pin configurations and uses.

aQFN73 ball assignments

The ball assignment figure and table in the following section describe the assignments for this variant of the chip.

Figure 1. aQFN73™ ball assignments, top view

aQFN73 ball assignments

Table 1. aQFN73 ball assignments
Pin Name Function Description Recommended usage
A8

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A10

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A12

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A14 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A16 P1.13 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A18 DEC2 Power 1.3 V regulator supply decoupling
A20 P1.10 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A22 VDD Power Power supply
A23 XC2 Analog input Connection for 32 MHz crystal
B1 VDD Power Power supply
B3 DCC Power DC/DC converter output
B5 DEC4 Power 1.3 V regulator supply decoupling Must be connected to DEC6 (pin E24)
B7 VSS Power Ground
B9

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B11

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B13

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B15 P1.14 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B17 P1.12 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B19 P1.11 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B24 XC1 Analog input Connection for 32 MHz crystal
C1 DEC1 Power 1.1 V regulator supply decoupling
D2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
D23 DEC3 Power Power supply, decoupling
E24 DEC6 Power 1.3 V regulator supply decoupling Must be connected to DEC4 (pin B5)
F2

P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
F23 VSS_PA Power Ground (radio supply)
G1 P0.26 Digital I/O General purpose I/O
H2 P0.27 Digital I/O General purpose I/O
H23 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
J1

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input
J24

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
K2

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input
L1 P0.06 Digital I/O General purpose I/O
L24

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
M2

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock
N1 P0.08 Digital I/O General purpose I/O
N24

DEC5

Not connected

 Power

1.3 V regulator supply decoupling for build codes Dxx and earlier.

Not connected for build codes Fxx and later.

P2 P1.08 Digital I/O General purpose I/O
P23 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O only
R1

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]
R24 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O only
T2

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]
T23 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O only
U1

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]
U24 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O only
V23 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O only
W1 VDD Power Power supply
W24 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O only
Y2 VDDH Power High voltage power supply
Y23 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O only
AA24 SWDCLK Debug Serial wire debug clock input for debug and programming
AB2 DCCH Power DC/DC converter output
AC5 DECUSB Power USB 3.3 V regulator supply decoupling
AC9 P0.14 Digital I/O General purpose I/O
AC11 P0.16 Digital I/O General purpose I/O
AC13

P0.18

nRESET

 Digital I/O

General purpose I/O

Configurable as pin RESET

 QSPI/CSN
AC15 P0.19 Digital I/O General purpose I/O QSPI/SCK
AC17 P0.21 Digital I/O General purpose I/O QSPI
AC19 P0.23 Digital I/O General purpose I/O QSPI
AC21 P0.25 Digital I/O General purpose I/O
AC24 SWDIO Debug Serial wire debug I/O for debug and programming
AD2 VBUS Power 5 V input for USB 3.3 V regulator
AD4 D- USB USB D-
AD6 D+ USB USB D+
AD8 P0.13 Digital I/O General purpose I/O
AD10 P0.15 Digital I/O General purpose I/O
AD12 P0.17 Digital I/O General purpose I/O
AD14 VDD Power Power supply
AD16 P0.20 Digital I/O General purpose I/O
AD18 P0.22 Digital I/O General purpose I/O QSPI
AD20 P0.24 Digital I/O General purpose I/O
AD22

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

 QSPI
AD23 VDD Power Power supply
Die pad VSS Power Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.

QFN48 pin assignments

The pin assignment figure and table describe the assignments for this variant of the chip.

Note: VDD and VDDH are shortcircuited inside the package. Therefore the device is only usable in Normal Voltage supply mode, and not High Voltage supply mode.
Figure 2. QFN48 pin assignments, top view


Table 2. QFN48 pin assignments
Pin Name Function Description Recommended usage
Left side of the chip
1 DEC1 Power 1.1 V Digital supply decoupling
2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
3

P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
4

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input
5

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input
6

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock
7 P0.08 Digital I/O General purpose I/O
8 P1.08 Digital I/O General purpose I/O
9

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]
10

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]
11

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]
12 VDD Power Power supply
Bottom side of chip
13 P0.13 Digital I/O General purpose I/O
14 P0.14 Digital I/O General purpose I/O
15 P0.17 Digital I/O General purpose I/O
16

P0.18

nRESET

 Digital I/O

General purpose I/O

Configurable as pin RESET

 QSPI/CSN
17 VDD Power Power supply
18 P0.19 Digital I/O General purpose I/O QSPI/SCK
19 P0.20 Digital I/O General purpose I/O
20 P0.21 Digital I/O General purpose I/O QSPI
21 P0.22 Digital I/O General purpose I/O QSPI
22 P0.23 Digital I/O General purpose I/O QSPI
23 P0.24 Digital I/O General purpose I/O
24

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

 QSPI
Right side of the chip
25 VDD Power Power supply
26 SWDIO Debug Serial wire debug I/O for debug and programming
27 SWDCLK Debug Serial wire debug clock input for debug and programming
28 NC Not connected
29

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
30

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
31 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
32 VSS_PA Power Ground (radio supply)
33 DEC6 Power 1.3 V regulator supply decoupling Must be connected to DEC4 (pin 46)
34 DEC3 Power Power supply, decoupling
35 XC1 Analog input Connection for 32 MHz crystal
36 XC2 Analog input Connection for 32 MHz crystal
Top side of the chip
37 VDD Power Power supply
38 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O only
39

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
40

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
41

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
42

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
43

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
44

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
45 VSS Power Ground
46 DEC4 Power 1.3 V regulator supply decoupling Must be connected to DEC6 (pin 33)
47 DCC Power DC/DC converter output
48 VDD Power Power supply
Backside of the chip
Die pad VSS Power Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation

WLCSP ball assignments

The ball assignment figure and table describe the assignments for this variant of the chip.

Figure 3. WLCSP ball assignments, top view

WLCSP ball assignments

Table 3. WLCSP ball assignments
Pin Name Function Description Recommended usage
A1 XC1 Analog input Connection for 32 MHz crystal
A2 XC2 Analog input Connection for 32 MHz crystal
A3 P1.11 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A4 P1.13 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A5

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A6

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A7

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A8 DEC4 Power

1.3 V regulator supply decoupling

Must be connected to DEC6 (pin C2)
A9 DCC Power DC/DC converter output
A10 DEC1 Power 1.1 V regulator supply decoupling
B3 VDD Power Power supply
B4 P1.10 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B5 P1.14 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B6

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B7 VSS Power Ground
B8 VDD Power Power supply
B9

P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
B10

P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal
C1 VSS_PA Power Ground (radio supply)
C2 DEC6 Power

1.3 V regulator supply decoupling

Must be connected to DEC4 (pin A8)
C4 VSS Power Ground
C5 P1.12 Digital I/O General purpose I/O Standard drive, low frequency I/O only
C6 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O only
C7

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
C8

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
C9 P0.26 Digital I/O General purpose I/O
C10

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input
D3 VSS Power Ground
D4 VSS Power Ground
D5 VSS Power Ground
D6 VSS Power Ground
D7 VSS Power Ground
D8 VSS Power Ground
D9 P0.27 Digital I/O General purpose I/O
D10

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input
E1 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
E2

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
E3 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O only
E4 VSS Power Ground
E5 VSS Power Ground
E6 VSS Power Ground
E7 VSS Power Ground
E8 VSS Power Ground
E9 P0.06 Digital I/O General purpose I/O
E10 P0.08 Digital I/O General purpose I/O
F1

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
F2

DEC5

Not connected

 Power

1.3 V regulator supply decoupling for build codes Dxx and earlier.

Not connected for build codes Fxx and later.

F3 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O only
F4 VSS Power Ground
F5 VSS Power Ground
F6 VSS Power Ground
F7 VSS Power Ground
F8 VSS Power Ground
F9

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock
F10

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]
G1 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G2 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G3 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G4 VSS Power Ground
G5 VSS Power Ground
G6 VSS Power Ground
G7 VSS Power Ground
G8 VSS Power Ground
G9 P1.08 Digital I/O General purpose I/O
G10

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]
H1 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O only
H2 SWDCLK Digital input Serial wire debug clock input for debug and programming
H4 P0.24 Digital I/O General purpose I/O
H5 P0.23 Digital I/O General purpose I/O QSPI
H6 P0.16 Digital I/O General purpose I/O
H7 P0.13 Digital I/O General purpose I/O
H8

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]
H9 DCCH Power DC/DC converter output
H10 VDD Power Power supply
J1 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O only
J2 SWDIO Digital I/O Serial wire debug I/O for debug and programming
J3

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

 QSPI
J4 P0.21 Digital I/O General purpose I/O QSPI
J5 P0.20 Digital I/O General purpose I/O
J6 P0.17 Digital I/O General purpose I/O
J7 P0.14 Digital I/O General purpose I/O
J8 D- USB USB D-
J9 VBUS Power 5 V input for USB 3.3 V regulator
J10 VDDH Power High voltage power supply
K1 VDD Power Power supply
K2 P0.25 Digital I/O General purpose I/O
K3 P0.22 Digital I/O General purpose I/O QSPI
K4 P0.19 Digital I/O General purpose I/O QSPI/SCK
K5 VDD Power Power supply
K6

P0.18

nRESET

Digital I/O

General purpose I/O

Configurable as pin reset

 QSPI/CSN
K7 P0.15 Digital I/O General purpose I/O
K8 D+ USB USB D+
K9 DECUSB Power USB 3.3 V regulator supply decoupling
K10 VSS Power Ground
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.