SAADC — Successive approximation analog-to-digital converter

The SAADC peripheral is a differential successive approximation register (SAR) analog-to-digital converter.

The main features of the SAADC are the following:

8/10/12-bit resolution, 14-bit resolution with oversampling
Up to eight channels for single-ended inputs and four channels for differential inputs, depending on the package variant
Full scale input range (0 V to VDD)
Multiple inputs
- Input pins AIN0 to AIN7
- VDD input
- VDDHDIV5 input
Individual reference selection for each channel
- VDD
- Internal reference
Continuous sampling
Output samples automatically stored in RAM using EasyDMA as 16-bit two's complement values
Internal resistor string

Channel and input configuration

Up to eight SAADC channels can be enabled and configured for SAADC.

A channel is connected to an analog input using the registers CH[n].PSELP and CH[n].PSELN. Each SAADC channel can be configured to use either single-ended mode or differential input mode. Setting register CH[n].PSELP enables the corresponding channel. Setting register CH[n].PSELN has no effect for single-ended channels.

Register CH[n].CONFIG configures SAADC channels. In Single-ended mode, the negative channel input is shorted to ground internally. In Single-ended mode, the assumption is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. This makes SAADC sensitive to ground bounce on the PCB. To avoid this, use the differential input mode instead.

Before sampling is started, the length and location of the memory buffer in RAM must be configured. Use registers RESULT.MAXCNT and RESULT.PTR to configure the length and location where the output values are to be written. The START task must be triggered to apply the configuration. See EasyDMA for details on memory configuration and how the results are stored in memory.

SAADC is stopped by triggering the STOP task. The STOP task also terminates the ongoing sampling. SAADC generates a STOPPED event when it has stopped. If SAADC is not started when the STOP task is triggered, the STOPPED event is still generated.

Shared resources

The SAADC peripheral shares analog resources with other analog peripherals.

While it is possible to use COMP and SAADC at the same time, selecting the same analog input pin for both peripherals is not supported.

Acquisition time

To sample input voltage, SAADC connects a capacitor to the input, as shown in the following figure.

Figure 2. Simplified SAADC sample network

Acquisition time is the amount of time the capacitor is connected, see the TACQ field in the CH[n].CONFIG register. The required acquisition time depends on the source resistance R_source. For high source resistance, increase the acquisition time according to the following table:

Table 1. Acquisition time
TACQ [µs]	Maximum source resistance [kΩ]
3	10
5	40
10	100
15	200
20	400
40	800

When using VDDHDIV5 as input, the acquisition time must be 10 µs or longer.

Internal resistor string (resistor ladder)

SAADC has an internal resistor string for positive and negative input. The resistors are controlled in register CH[n].CONFIG.

The following figure illustrates the resistor ladder for positive and negative input:

Figure 3. Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP)

Reference voltage and gain settings

Each SAADC channel can have individual reference and gain settings. These settings are configured in register CH[n].CONFIG.

The following configuration options are available:

VDD/4 or internal 0.6 V reference
Gain ranging from 1/6 to 4

The gain setting controls the effective input range of SAADC, as shown in the following equation:

Input range = (±0.6 V or ±VDD/4)/gain

For example, selecting VDD as reference, single-ended input (grounded negative input), and a gain of 1/4 gives the following input range:

Input range = (VDD/4)/(1/4) = VDD

With internal reference, single-ended input (grounded negative input) and a gain of 1/6, the input range is the following:

Input range = (0.6 V)/(1/6) = 3.6 V

Inputs AIN0 to AIN7 cannot exceed VDD or be lower than VSS.

Operation modes

The SAADC configuration supports Single-channel Single Conversion mode, Single-channel Continuous Conversion mode, and scan mode. Only one mode can be enabled at a time.

Single-channel sampling happens in either Single Conversion mode or Continuous Conversion mode. Scan mode is entered when more than one channel is enabled.

Oversampling can be used to improve the signal-to-noise ratio (SNR). It is not recommended to use oversampling for scan mode. For more information about oversampling, see Oversampling.

Single-channel Single Conversion mode

SAADC performs one conversion of a single channel and stops once complete.

This mode of operation is configured by enabling only one of the available channels defined by the registers CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG. When the SAMPLE task is triggered, SAADC starts sampling the input voltage.

A DONE event signals that the sample was taken. In this mode, the RESULTDONE and DONE events are equal when oversampling does not happen. Both events can occur before EasyDMA transfers the value to RAM. For more information, see EasyDMA. The END event is generated when RESULT.MAXCNT values are transferred to RAM.

Single-channel Continuous Conversion mode

In Single-channel Continuous Conversion mode, a single channel is sampled continuously.

Continuous sampling is achieved with an internal timer in the SAADC peripheral. The register SAMPLERATE configures the Single-channel Continuous Conversion mode and sample rate.

The sample rate must fulfill the following criteria:

 f_SAMPLE < 1 / (t_ACQ + t_conv)

When Single-channel Continuous Conversion mode is selected, SAADC is started by triggering the SAMPLE task once. Triggering the STOP task stops sampling. A DONE event signals that one sample was taken. In this mode, the RESULTDONE and DONE events are equal when oversampling does not happen. Both events may occur before EasyDMA transfers the value to RAM. For more information, see EasyDMA. The END event is generated when RESULT.MAXCNT values are transferred to RAM.

Scan mode

If more than one channel is enabled, SAADC functions in scan mode.

In scan mode, one SAMPLE task triggers one conversion per enabled channel.

The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time t_ACQ and the conversion time t_CONV.

The events DONE and RESULTDONE are generated when one sample is taken. Both events may occur before EasyDMA transfers the values into RAM, see EasyDMA for more information.

Note: Continuous conversion mode is not supported in scan mode.

Oversampling

An accumulator in SAADC can be used to find the average of several analog input samples. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling does not improve the integral non-linearity (INL) or differential non-linearity (DNL).

Oversampling is configured in register OVERSAMPLE. When oversampling, 2^OVERSAMPLE samples are averaged before one result is transferred to memory. The mode used to sample the input determines when and how those samples are taken.

When oversampling is configured, DONE event is generated for every input sample taken. RESULTDONE event is generated for every averaged value ready to be transferred into RAM. END event is generated when RESULT.MAXCNT averaged values are transferred into RAM.

Note: Oversampling should only be used when a single input channel is enabled, as averaging is performed over all enabled channels.

Digital output

The digital output value is calculated using the following formula.

RESULT = [V(P) – V(N)] * (GAIN/REFERENCE) * 2^{(RESOLUTION - m)}

where V(P) is the voltage at input P, V(N) is the voltage at input N, GAIN is the selected gain, REFERENCE is the selected reference voltage, RESOLUTION is output resolution in bits, as configured in register RESOLUTION, and m being 0 for single-ended channels and 1 for differential channels.

Results are sign extended to 16 bits and stored in RAM in little-endian byte order.

Results generated by SAADC deviate due to DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the gain block, settling errors due to high source impedance, and sampling jitter. DC errors affect the most for battery measurement.

EasyDMA

SAADC resources are started by triggering the START task. The SAADC uses EasyDMA to store results in a buffer in RAM.

Registers RESULT.PTR and RESULT.MAXCNT must be configured before SAADC is started.

The result buffer is located at the address specified in register RESULT.PTR. This register is double-buffered, and it can be updated and prepared for the next START task immediately after the STARTED event is generated. Register RESULT.MAXCNT specifies the size of the result buffer. SAADC generates an END event when the result buffer is full, as shown in the following figure.

The following figure provides an example of results in Data RAM with an even RESULT.MAXCNT and channels 1, 2, and 5 enabled.

Figure 5. Example of RAM placement (even RESULT.MAXCNT), channels 1, 2, and 5 enabled

The following figure provides an example of results in Data RAM with an odd RESULT.MAXCNT and channels 1, 2, and 5 enabled.

Figure 6. Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2, and 5 enabled

The last 32-bit word is populated with only one 16-bit result.

See Memory for more information about the different memory regions.

EasyDMA is finished accessing RAM when events END or STOPPED are generated. To see the number of results transferred to the RAM result buffer since the START task was triggered, read register RESULT.AMOUNT.

Event monitoring using limits

Using limits allows event monitoring on channels.

A high and low limit can be configured in the CH[n].LIMIT register. The high limit must be higher than or equal to the low limit.

Relevant events are generated when the conversion results (sampled input signals) are outside of the defined limits. It is not possible to generate an event when the input signal is inside a defined range by switching the high and low limit. An example of event monitoring using limits is illustrated in the following figure:

Example: Event monitoring on channel n using limits — Figure 7. Event monitoring on channel[n] using limits

Limit comparison does not need to be enabled. If event monitoring is not required, related events should be ignored.

Calibration

The SAADC peripheral has a temperature dependent offset.

It is recommended to calibrate SAADC at least once before use, and recalibrate when the ambient temperature changes by more than 10°C.

Offset calibration is started by triggering the CALIBRATEOFFSET task. The CALIBRATEDONE event is generated when calibration is finished.

Registers

Instances


Instance	Base address	Description
SAADC	0x40007000	Analog to digital converter

Register overview


Register	Offset	Description
TASKS_START	0x000	Starts the SAADC and prepares the result buffer in RAM
TASKS_SAMPLE	0x004	Takes one SAADC sample
TASKS_STOP	0x008	Stops the SAADC and terminates all on-going conversions
TASKS_CALIBRATEOFFSET	0x00C	Starts offset auto-calibration
EVENTS_STARTED	0x100	The SAADC has started
EVENTS_END	0x104	The SAADC has filled up the result buffer
EVENTS_DONE	0x108	A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
EVENTS_RESULTDONE	0x10C	Result ready for transfer to RAM
EVENTS_CALIBRATEDONE	0x110	Calibration is complete
EVENTS_STOPPED	0x114	The SAADC has stopped
EVENTS_CH[0].LIMITH	0x118	Last result is equal or above CH[0].LIMIT.HIGH
EVENTS_CH[0].LIMITL	0x11C	Last result is equal or below CH[0].LIMIT.LOW
EVENTS_CH[1].LIMITH	0x120	Last result is equal or above CH[1].LIMIT.HIGH
EVENTS_CH[1].LIMITL	0x124	Last result is equal or below CH[1].LIMIT.LOW
EVENTS_CH[2].LIMITH	0x128	Last result is equal or above CH[2].LIMIT.HIGH
EVENTS_CH[2].LIMITL	0x12C	Last result is equal or below CH[2].LIMIT.LOW
EVENTS_CH[3].LIMITH	0x130	Last result is equal or above CH[3].LIMIT.HIGH
EVENTS_CH[3].LIMITL	0x134	Last result is equal or below CH[3].LIMIT.LOW
EVENTS_CH[4].LIMITH	0x138	Last result is equal or above CH[4].LIMIT.HIGH
EVENTS_CH[4].LIMITL	0x13C	Last result is equal or below CH[4].LIMIT.LOW
EVENTS_CH[5].LIMITH	0x140	Last result is equal or above CH[5].LIMIT.HIGH
EVENTS_CH[5].LIMITL	0x144	Last result is equal or below CH[5].LIMIT.LOW
EVENTS_CH[6].LIMITH	0x148	Last result is equal or above CH[6].LIMIT.HIGH
EVENTS_CH[6].LIMITL	0x14C	Last result is equal or below CH[6].LIMIT.LOW
EVENTS_CH[7].LIMITH	0x150	Last result is equal or above CH[7].LIMIT.HIGH
EVENTS_CH[7].LIMITL	0x154	Last result is equal or below CH[7].LIMIT.LOW
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
STATUS	0x400	Status
ENABLE	0x500	Enable or disable SAADC
CH[0].PSELP	0x510	Input positive pin selection for CH[0]
CH[0].PSELN	0x514	Input negative pin selection for CH[0]
CH[0].CONFIG	0x518	Input configuration for CH[0]
CH[0].LIMIT	0x51C	High/low limits for event monitoring of a channel
CH[1].PSELP	0x520	Input positive pin selection for CH[1]
CH[1].PSELN	0x524	Input negative pin selection for CH[1]
CH[1].CONFIG	0x528	Input configuration for CH[1]
CH[1].LIMIT	0x52C	High/low limits for event monitoring of a channel
CH[2].PSELP	0x530	Input positive pin selection for CH[2]
CH[2].PSELN	0x534	Input negative pin selection for CH[2]
CH[2].CONFIG	0x538	Input configuration for CH[2]
CH[2].LIMIT	0x53C	High/low limits for event monitoring of a channel
CH[3].PSELP	0x540	Input positive pin selection for CH[3]
CH[3].PSELN	0x544	Input negative pin selection for CH[3]
CH[3].CONFIG	0x548	Input configuration for CH[3]
CH[3].LIMIT	0x54C	High/low limits for event monitoring of a channel
CH[4].PSELP	0x550	Input positive pin selection for CH[4]
CH[4].PSELN	0x554	Input negative pin selection for CH[4]
CH[4].CONFIG	0x558	Input configuration for CH[4]
CH[4].LIMIT	0x55C	High/low limits for event monitoring of a channel
CH[5].PSELP	0x560	Input positive pin selection for CH[5]
CH[5].PSELN	0x564	Input negative pin selection for CH[5]
CH[5].CONFIG	0x568	Input configuration for CH[5]
CH[5].LIMIT	0x56C	High/low limits for event monitoring of a channel
CH[6].PSELP	0x570	Input positive pin selection for CH[6]
CH[6].PSELN	0x574	Input negative pin selection for CH[6]
CH[6].CONFIG	0x578	Input configuration for CH[6]
CH[6].LIMIT	0x57C	High/low limits for event monitoring of a channel
CH[7].PSELP	0x580	Input positive pin selection for CH[7]
CH[7].PSELN	0x584	Input negative pin selection for CH[7]
CH[7].CONFIG	0x588	Input configuration for CH[7]
CH[7].LIMIT	0x58C	High/low limits for event monitoring of a channel
RESOLUTION	0x5F0	Resolution configuration
OVERSAMPLE	0x5F4	Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
SAMPLERATE	0x5F8	Controls normal or continuous sample rate
RESULT.PTR	0x62C	Data pointer
RESULT.MAXCNT	0x630	Maximum number of 16-bit samples to be written to output RAM buffer
RESULT.AMOUNT	0x634	Number of 16-bit samples written to output RAM buffer since the previous START task

TASKS_START

Address offset: 0x000

Starts the SAADC and prepares the result buffer in RAM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_START										Starts the SAADC and prepares the result buffer in RAM
			Trigger	1								Trigger task

TASKS_SAMPLE

Address offset: 0x004

Takes one SAADC sample


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_SAMPLE										Takes one SAADC sample
			Trigger	1								Trigger task

TASKS_STOP

Address offset: 0x008

Stops the SAADC and terminates all on-going conversions


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_STOP										Stops the SAADC and terminates all on-going conversions
			Trigger	1								Trigger task

TASKS_CALIBRATEOFFSET

Address offset: 0x00C

Starts offset auto-calibration


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CALIBRATEOFFSET										Starts offset auto-calibration
			Trigger	1								Trigger task

EVENTS_STARTED

Address offset: 0x100

The SAADC has started


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_STARTED										The SAADC has started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_END

Address offset: 0x104

The SAADC has filled up the result buffer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_END										The SAADC has filled up the result buffer
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DONE

Address offset: 0x108

A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_DONE										A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_RESULTDONE

Address offset: 0x10C

Result ready for transfer to RAM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_RESULTDONE										Result ready for transfer to RAM
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CALIBRATEDONE

Address offset: 0x110

Calibration is complete


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_CALIBRATEDONE										Calibration is complete
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_STOPPED

Address offset: 0x114

The SAADC has stopped


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_STOPPED										The SAADC has stopped
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[0]

Peripheral events.

EVENTS_CH[0].LIMITH

Address offset: 0x118

Last result is equal or above CH[0].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[0].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[0].LIMITL

Address offset: 0x11C

Last result is equal or below CH[0].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[0].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[1]

Peripheral events.

EVENTS_CH[1].LIMITH

Address offset: 0x120

Last result is equal or above CH[1].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[1].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[1].LIMITL

Address offset: 0x124

Last result is equal or below CH[1].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[1].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[2]

Peripheral events.

EVENTS_CH[2].LIMITH

Address offset: 0x128

Last result is equal or above CH[2].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[2].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[2].LIMITL

Address offset: 0x12C

Last result is equal or below CH[2].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[2].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[3]

Peripheral events.

EVENTS_CH[3].LIMITH

Address offset: 0x130

Last result is equal or above CH[3].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[3].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[3].LIMITL

Address offset: 0x134

Last result is equal or below CH[3].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[3].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[4]

Peripheral events.

EVENTS_CH[4].LIMITH

Address offset: 0x138

Last result is equal or above CH[4].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[4].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[4].LIMITL

Address offset: 0x13C

Last result is equal or below CH[4].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[4].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[5]

Peripheral events.

EVENTS_CH[5].LIMITH

Address offset: 0x140

Last result is equal or above CH[5].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[5].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[5].LIMITL

Address offset: 0x144

Last result is equal or below CH[5].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[5].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[6]

Peripheral events.

EVENTS_CH[6].LIMITH

Address offset: 0x148

Last result is equal or above CH[6].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[6].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[6].LIMITL

Address offset: 0x14C

Last result is equal or below CH[6].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[6].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[7]

Peripheral events.

EVENTS_CH[7].LIMITH

Address offset: 0x150

Last result is equal or above CH[7].LIMIT.HIGH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITH										Last result is equal or above CH[7].LIMIT.HIGH
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CH[7].LIMITL

Address offset: 0x154

Last result is equal or below CH[7].LIMIT.LOW


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LIMITL										Last result is equal or below CH[7].LIMIT.LOW
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID														V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	STARTED										Enable or disable interrupt for event STARTED
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	END										Enable or disable interrupt for event END
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	DONE										Enable or disable interrupt for event DONE
			Disabled	0								Disable
			Enabled	1								Enable
D	RW	RESULTDONE										Enable or disable interrupt for event RESULTDONE
			Disabled	0								Disable
			Enabled	1								Enable
E	RW	CALIBRATEDONE										Enable or disable interrupt for event CALIBRATEDONE
			Disabled	0								Disable
			Enabled	1								Enable
F	RW	STOPPED										Enable or disable interrupt for event STOPPED
			Disabled	0								Disable
			Enabled	1								Enable
G	RW	CH0LIMITH										Enable or disable interrupt for event CH0LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
H	RW	CH0LIMITL										Enable or disable interrupt for event CH0LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
I	RW	CH1LIMITH										Enable or disable interrupt for event CH1LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
J	RW	CH1LIMITL										Enable or disable interrupt for event CH1LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
K	RW	CH2LIMITH										Enable or disable interrupt for event CH2LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
L	RW	CH2LIMITL										Enable or disable interrupt for event CH2LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
M	RW	CH3LIMITH										Enable or disable interrupt for event CH3LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
N	RW	CH3LIMITL										Enable or disable interrupt for event CH3LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
O	RW	CH4LIMITH										Enable or disable interrupt for event CH4LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
P	RW	CH4LIMITL										Enable or disable interrupt for event CH4LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
Q	RW	CH5LIMITH										Enable or disable interrupt for event CH5LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
R	RW	CH5LIMITL										Enable or disable interrupt for event CH5LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
S	RW	CH6LIMITH										Enable or disable interrupt for event CH6LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
T	RW	CH6LIMITL										Enable or disable interrupt for event CH6LIMITL
			Disabled	0								Disable
			Enabled	1								Enable
U	RW	CH7LIMITH										Enable or disable interrupt for event CH7LIMITH
			Disabled	0								Disable
			Enabled	1								Enable
V	RW	CH7LIMITL										Enable or disable interrupt for event CH7LIMITL
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID														V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	STARTED										Write '1' to enable interrupt for event STARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	END										Write '1' to enable interrupt for event END
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	DONE										Write '1' to enable interrupt for event DONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	RESULTDONE										Write '1' to enable interrupt for event RESULTDONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	CALIBRATEDONE										Write '1' to enable interrupt for event CALIBRATEDONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	STOPPED										Write '1' to enable interrupt for event STOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW	CH0LIMITH										Write '1' to enable interrupt for event CH0LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	CH0LIMITL										Write '1' to enable interrupt for event CH0LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW	CH1LIMITH										Write '1' to enable interrupt for event CH1LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW	CH1LIMITL										Write '1' to enable interrupt for event CH1LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW	CH2LIMITH										Write '1' to enable interrupt for event CH2LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW	CH2LIMITL										Write '1' to enable interrupt for event CH2LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW	CH3LIMITH										Write '1' to enable interrupt for event CH3LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW	CH3LIMITL										Write '1' to enable interrupt for event CH3LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW	CH4LIMITH										Write '1' to enable interrupt for event CH4LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW	CH4LIMITL										Write '1' to enable interrupt for event CH4LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW	CH5LIMITH										Write '1' to enable interrupt for event CH5LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW	CH5LIMITL										Write '1' to enable interrupt for event CH5LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW	CH6LIMITH										Write '1' to enable interrupt for event CH6LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW	CH6LIMITL										Write '1' to enable interrupt for event CH6LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW	CH7LIMITH										Write '1' to enable interrupt for event CH7LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW	CH7LIMITL										Write '1' to enable interrupt for event CH7LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID														V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	STARTED										Write '1' to disable interrupt for event STARTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	END										Write '1' to disable interrupt for event END
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	DONE										Write '1' to disable interrupt for event DONE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	RESULTDONE										Write '1' to disable interrupt for event RESULTDONE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	CALIBRATEDONE										Write '1' to disable interrupt for event CALIBRATEDONE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	STOPPED										Write '1' to disable interrupt for event STOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW	CH0LIMITH										Write '1' to disable interrupt for event CH0LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	CH0LIMITL										Write '1' to disable interrupt for event CH0LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW	CH1LIMITH										Write '1' to disable interrupt for event CH1LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW	CH1LIMITL										Write '1' to disable interrupt for event CH1LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW	CH2LIMITH										Write '1' to disable interrupt for event CH2LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW	CH2LIMITL										Write '1' to disable interrupt for event CH2LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW	CH3LIMITH										Write '1' to disable interrupt for event CH3LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW	CH3LIMITL										Write '1' to disable interrupt for event CH3LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW	CH4LIMITH										Write '1' to disable interrupt for event CH4LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW	CH4LIMITL										Write '1' to disable interrupt for event CH4LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW	CH5LIMITH										Write '1' to disable interrupt for event CH5LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW	CH5LIMITL										Write '1' to disable interrupt for event CH5LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW	CH6LIMITH										Write '1' to disable interrupt for event CH6LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW	CH6LIMITL										Write '1' to disable interrupt for event CH6LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW	CH7LIMITH										Write '1' to disable interrupt for event CH7LIMITH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW	CH7LIMITL										Write '1' to disable interrupt for event CH7LIMITL
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

STATUS

Address offset: 0x400

Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	STATUS										Status
			Ready	0								SAADC is ready. No on-going conversions.
			Busy	1								SAADC is busy. Conversion in progress.

ENABLE

Address offset: 0x500

Enable or disable SAADC


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable or disable SAADC
			Disabled	0								Disable SAADC
			Enabled	1								Enable SAADC When enabled, the SAADC will acquire access to analog input pins specified in registers CH[n].PSELP and CH[n].PSELN

CH[0].PSELP

Address offset: 0x510

Input positive pin selection for CH[0]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[0].PSELN

Address offset: 0x514

Input negative pin selection for CH[0]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[0].CONFIG

Address offset: 0x518

Input configuration for CH[0]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[0].LIMIT

Address offset: 0x51C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[1].PSELP

Address offset: 0x520

Input positive pin selection for CH[1]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[1].PSELN

Address offset: 0x524

Input negative pin selection for CH[1]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[1].CONFIG

Address offset: 0x528

Input configuration for CH[1]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[1].LIMIT

Address offset: 0x52C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[2].PSELP

Address offset: 0x530

Input positive pin selection for CH[2]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[2].PSELN

Address offset: 0x534

Input negative pin selection for CH[2]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[2].CONFIG

Address offset: 0x538

Input configuration for CH[2]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[2].LIMIT

Address offset: 0x53C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[3].PSELP

Address offset: 0x540

Input positive pin selection for CH[3]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[3].PSELN

Address offset: 0x544

Input negative pin selection for CH[3]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[3].CONFIG

Address offset: 0x548

Input configuration for CH[3]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[3].LIMIT

Address offset: 0x54C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[4].PSELP

Address offset: 0x550

Input positive pin selection for CH[4]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[4].PSELN

Address offset: 0x554

Input negative pin selection for CH[4]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[4].CONFIG

Address offset: 0x558

Input configuration for CH[4]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[4].LIMIT

Address offset: 0x55C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[5].PSELP

Address offset: 0x560

Input positive pin selection for CH[5]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[5].PSELN

Address offset: 0x564

Input negative pin selection for CH[5]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[5].CONFIG

Address offset: 0x568

Input configuration for CH[5]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[5].LIMIT

Address offset: 0x56C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[6].PSELP

Address offset: 0x570

Input positive pin selection for CH[6]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[6].PSELN

Address offset: 0x574

Input negative pin selection for CH[6]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[6].CONFIG

Address offset: 0x578

Input configuration for CH[6]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[6].LIMIT

Address offset: 0x57C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

CH[7].PSELP

Address offset: 0x580

Input positive pin selection for CH[7]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELP										Analog positive input channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[7].PSELN

Address offset: 0x584

Input negative pin selection for CH[7]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PSELN										Analog negative input, enables differential channel
			NC	0								Not connected
			AnalogInput0	1								AIN0
			AnalogInput1	2								AIN1
			AnalogInput2	3								AIN2
			AnalogInput3	4								AIN3
			AnalogInput4	5								AIN4
			AnalogInput5	6								AIN5
			AnalogInput6	7								AIN6
			AnalogInput7	8								AIN7
			VDD	9								VDD
			VDDHDIV5	0x0D								VDDH/5

CH[7].CONFIG

Address offset: 0x588

Input configuration for CH[7]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the SAADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

CH[7].LIMIT

Address offset: 0x58C

High/low limits for event monitoring of a channel


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x7FFF8000				0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOW		[-32768 to +32767]								Low level limit
B	RW	HIGH		[-32768 to +32767]								High level limit

RESOLUTION

Address offset: 0x5F0

Resolution configuration


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Set the resolution
			8bit	0								8 bits
			10bit	1								10 bits
			12bit	2								12 bits
			14bit	3								14 bits

OVERSAMPLE

Address offset: 0x5F4

Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OVERSAMPLE										Oversample control
			Bypass	0								Bypass oversampling
			Over2x	1								Oversample 2x
			Over4x	2								Oversample 4x
			Over8x	3								Oversample 8x
			Over16x	4								Oversample 16x
			Over32x	5								Oversample 32x
			Over64x	6								Oversample 64x
			Over128x	7								Oversample 128x
			Over256x	8								Oversample 256x

SAMPLERATE

Address offset: 0x5F8

Controls normal or continuous sample rate


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																							B		A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CC		[80..2047]								Capture and compare value. Sample rate is 16 MHz/CC
B	RW	MODE										Select mode for sample rate control
			Task	0								Rate is controlled from SAMPLE task
			Timers	1								Rate is controlled from local timer (use CC to control the rate)

RESULT

RESULT EasyDMA channel

RESULT.PTR

Address offset: 0x62C

Data pointer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PTR										Data pointer Note: See Memory for details about memories available to EasyDMA.

RESULT.MAXCNT

Address offset: 0x630

Maximum number of 16-bit samples to be written to output RAM buffer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MAXCNT										Maximum number of 16-bit samples to be written to output RAM buffer

RESULT.AMOUNT

Address offset: 0x634

Number of 16-bit samples written to output RAM buffer since the previous START task


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	AMOUNT										Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event.

Electrical specification

SAADC electrical specification


Symbol	Description	Min.	Typ.	Max.	Units
DNL₁₀	Differential non-linearity, 10-bit resolution	-0.95	<1		LSB10b
INL₁₀	Integral non-linearity, 10-bit resolution		1		LSB10b
DNL₁₂	Differential non-linearity, 12-bit resolution	-0.95	1.3		LSB12b
INL₁₂	Integral non-linearity, 12-bit resolution		4.7		LSB12b
V_OS	Differential offset error (calibrated), 10-bit resolution ^¹		±2		LSB10b
E_VDDHDIV5	Error on VDDHDIV5 input		±1		%
C_EG	Gain error temperature coefficient		0.02		%/◦C
f_SAMPLE	Maximum sampling rate			200	kHz
t_CONV	Conversion time		<2		µs
E_G1/6	Error^² for gain = 1/6	-3		3	%
E_G1/4	Error^² for gain = 1/4	-3		3	%
E_G1/2	Error^² for gain = 1/2	-3		4	%
E_G1	Error^² for gain = 1	-3		4	%
C_SAMPLE	Sample and hold capacitance at maximum gain³		2.5		pF
R_INPUT	Input resistance		>1		MΩ
E_NOB	Effective number of bits, differential mode, 12-bit resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200 ksps		9		Bit
S_NDR	Peak signal to noise and distortion ratio, differential mode, 12-bit resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200 ksps		56		dB
S_FDR	Spurious free dynamic range, differential mode, 12-bit resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200 ksps		70		dBc
R_LADDER	Ladder resistance		160		kΩ

¹ Digital output code at zero volt differential input.

² Does not include temperature drift

³ Maximum gain corresponds to highest capacitance.