TIMER can be used in the following ways, depending on configuration.

  • Boot monitor
  • Watchdog timer
  • Wake-up timer
  • General purpose timer
TIMER is a 24-bit timer running at the frequency of the timer clock, fTIMER, and has a prescaler.

TIMER only runs one configuration at a time because it is shared for all functions. The wake-up timer wakes the system at a programmable interval when the device is in Hibernate mode. Do not use the watchdog timer or general purpose timer when the system is in Ship or Hibernate mode.

TIMER is controlled by register TIMERCONFIG. The start value is configured with TIMERHIBYTE, TIMERMIDBYTE, and TIMERLOBYTE. The settings are applied with TIMERTARGETSTROBE. TIMER is started with TIMERSET and is stopped with TIMERCLR.

Example settings are shown in the following table.
Table 1. Example timer register settings
fTIMER TIMERHIBYTE TIMERMIDBYTE TIMERLOBYTE Time
2 ms 0 0 250 0.5 s
16 ms 0 0 250 4 s
16 ms 0 1 0 4.096 s
16 ms 1 0 0 1048.576 s
16 ms 255 255 255 74.5 h

Boot monitor

After a power-on reset, the default timer is boot monitor and this is disabled. When enabled, it allows an automatic power cycle if the host does not set bit TASK.TIMER.DIS within tBOOT.

Host software can enable the boot monitor with bit BOOT.TIMER.EN. It can disable the boot monitor to prevent interference with firmware updates. When enabled, the boot monitor remains enabled even if the chip is reset, except for a power-on reset. Removing both VBAT and VBUS, or clearing the BOOT.TIMER.EN bit, deactivates the timer during the next power-up.

Watchdog timer

Watchdog timer expiration can be configured by host software to generate an NRESETOUT through a GPIO or a power cycle.

Power cycle means internally disconnecting VSYS from VBAT and VBUS. BUCK and LOADSW are actively pulled low for 100 ms. The device is reset and BUCK is re-enabled. Active pull-downs are present at pin VOUT1, VOUT2, LSOUT1, and LS2OUT2 during tPWRDN.

The watchdog timer can issue a pre-warning interrupt, tPREWARN, before expiration. The reset pulse, which is active-low, through the NRESETOUT GPIO lasts for tRESET. Watchdog can be configured in register WATCHDOGKICK.

The pre-warning interrupt is generated one cycle of the selected prescaler, either 2 ms or 16 ms, before expiry of the watchdog occurs.

The following figure shows a watchdog reset where the nPM1300 device is not reset internally.

Figure 1. Watchdog reset
Page-1 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 VSYS VSYS Sheet.13 LSOUT[n] (LOADSW) LSOUT[n] (LOADSW) Sheet.14 VOUT[n] (BUCK) VOUT[n] (BUCK) Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Watchdog expires Watchdog expires Sheet.26 Normal Normal Sheet.27 Sheet.28 tRESET tRESET Sheet.29 Normal Normal Sheet.30 Sheet.31 Sheet.33 NRESETOUT (GPIO) NRESETOUT (GPIO)
Figure 2. Power cycle
Power cycle
Note: For the thermal shutdown case, tPWRDN will be longer as it waits for the die temperature to cool down below TSD - TSDHYST.

Wake-up timer

The wake-up timer wakes the system from Hibernate mode.

Host software configures the timer before the device enters Hibernate mode, see Ship and Hibernate modes.

General purpose timer

The general purpose timer interrupts the host after a timeout with the WATCHDOG.WARNING event.

Prescaler is configured in register TIMERCONFIG with the default set to 16 ms.

When the prescaler is configured to 16 ms in TIMERCONFIG and TIMERHIBYTE is 5, TIMERMIDBYTE is 2 and TIMERLOBYTE is 1, then the general purpose timer will wake after 5251 seconds.

Electrical specification

Both prescaler settings 16 ms and (2 ms) are included. Values in parenthesis are for the 2 ms prescaler.

Table 2. TIMER electrical specification
Symbol Description Min. Typ. Max. Unit
fTIMER Frequency of timer clock 64

(512)

 Hz
tPREWARN Time between watchdog timer interrupt and reset/power cycle 16

(2)

 ms
tPER_MIN Minimum time period 16

(2)

 ms
tPER_MAX Maximum time period 3

(9)

 days

(hours)
tBOOT Amount of time before a power cycle is performed when no traffic is observed on TWI and BOOT.TIMER.EN is set 10 s
tPWRDN Length of power cycle 100 ms
tRESET Length of reset pulse 100 ms
fACCUR Accuracy of timer clock ±3 %

Registers

Instances

Instance Base address Description
TIMER 0x00000700

TIMER registers

TIMER register map

Register overview

Register Offset Description
TIMERSET 0x0

Start timer
TIMERCLR 0x1

Stop timer
TIMERTARGETSTROBE 0x3

Strobe for timer target
WATCHDOGKICK 0x4

Watchdog kick
TIMERCONFIG 0x5

Timer mode selection
TIMERSTATUS 0x6

Timers status
TIMERHIBYTE 0x8

Timer most significant byte
TIMERMIDBYTE 0x9

Timer middle byte
TIMERLOBYTE 0xA

Timer least significant byte

TIMERSET

Address offset: 0x0

Start timer

Bit number 7 6 5 4 3 2 1 0
ID A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKTIMEREN

Start timer

NOEFFECT

0

No effect

SET

1

Timer start request

TIMERCLR

Address offset: 0x1

Stop timer

Bit number 7 6 5 4 3 2 1 0
ID A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKTIMERDIS

Stop timer

NOEFFECT

0

No effect

SET

1

Timer stop request

TIMERTARGETSTROBE

Address offset: 0x3

Strobe for timer target

Bit number 7 6 5 4 3 2 1 0
ID A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKTIMERTARGETSTROBE

Timer target strobe

NOEFFECT

0

No effect

SET

1

Load timer target (24-bit timer value)

WATCHDOGKICK

Address offset: 0x4

Watchdog kick

Bit number 7 6 5 4 3 2 1 0
ID A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKWATCHDOGKICK

Watchdog kick

NOEFFECT

0

No effect

Kick

1

Kick watchdog

TIMERCONFIG

Address offset: 0x5

Timer mode selection

Bit number 7 6 5 4 3 2 1 0
ID B A A A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TIMERMODESEL

Select watchdog and timer modes

BOOTMONITOR

0

Boot monitor

WATCHDOGWARNING

1

Watchdog warning

WATCHDOGRESET

2

Watchdog reset

GENPURPOSETIMER

3

General purpose timer

WAKEUPTIMER

4

Wakeup timer
B

RW

TIMERPRESCALER

Select between 16 ms and 2 ms timer prescaler

SLOW

0

16 ms prescaler

FAST

1

2 ms prescaler

TIMERSTATUS

Address offset: 0x6

Timers status

Bit number 7 6 5 4 3 2 1 0
ID B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

BOOTMONITORACTIVE

Boot monitor active

INACTIVE

0

Boot monitor not running

ACTIVE

1

Boot monitor running
B

R

SLOWDOMAINCONFIGURED

Timer ready after TIMERTARGETSTROBE

NOTCONFIG

0

Not configured

CONFIG

1

Timer configured

TIMERHIBYTE

Address offset: 0x8

Timer most significant byte

Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TIMERHIBYTE

Timer most significant byte

TIMERMIDBYTE

Address offset: 0x9

Timer middle byte

Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TIMERMIDBYTE

Timer middle byte

TIMERLOBYTE

Address offset: 0xA

Timer least significant byte

Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TIMERLOBYTE

Timer least significant byte