Control and register interfaces

TWI — Two-Wire Interface

TWI is the main interface to control and monitor the device state through registers.

The following are the TWI main features:

I2C compatible
TWI clock 100 kHz - 400 kHz supported
Slave device with 7-bit slave address
Clock stretching not supported
General Call address not supported
Software Reset not supported
Device ID not supported

TWI slave address

The TWI 7-bit slave-address value is 1110000b = 0x70h.

TWI electrical specification

Table 1. TWI electrical specification
Symbol	Description	Min.	Typ.	Max.	Units
F_SCL	Clock frequency	100		400	kHz
T_SU_DAT_100K	Data setup time before positive edge on SCL,100 kbps	250			ns
T_SU_DAT_400K	Data setup time before positive edge on SCL, 400 kbps	100			ns
T_HD_DAT	Data hold time after negative edge on SCL, all modes	0			ns
T_HD_STA_100K	Hold time from for START condition (SDA low to SCL low), 100 kbps	4000			ns
T_HD_STA_400K	Hold time from for START condition (SDA low to SCL low), 400 kbps	600			ns
T_SU_STO_100K	Setup time from SCL high to STOP condition, 100 kbps	4000			ns
T_SU_STO_400K	Setup time from SCL high to STOP condition, 400 kbps	600			ns
T_BUF_100K	Bus free time between STOP and START conditions, 100 kbps		4700		ns
T_BUF_400K	Bus free time between STOP and START conditions, 400 kbps		1300		ns

TWI timing diagram

Figure 1. TWI timing diagram

Registers

Instances


Instance	Base address	Description
DIGITAL	0x00000000	nPM6001 registers

Register overview


Register	Offset	Description
SWREADY	0x01	Software ready
TASKS_START_BUCK3	0x02	Start BUCK3
TASKS_START_LDO0	0x03	Start LDO0
TASKS_START_LDO1	0x04	Start LDO1
TASKS_START_THWARN	0x06	Start thermal warning sensor
TASKS_START_TH_SHUTDN	0x07	Start thermal shutdown sensor
TASKS_STOP_BUCK3	0x08	Stop BUCK3
TASKS_STOP_LDO0	0x09	Stop LDO0
TASKS_STOP_LDO1	0x0A	Stop LDO1
TASKS_STOP_THWARN	0x0C	Stop thermal warning sensor
TASKS_STOP_THSHUTDN	0x0D	Stop thermal shutdown sensor
TASKS_UPDATE_VOUTPWM	0x0E	Update output voltage settings for BUCK0, BUCK1 and BUCK2
EVENTS_THWARN	0x1E	Thermal warning event
EVENTS_BUCK0OC	0x1F	BUCK0 overcurrent event
EVENTS_BUCK1OC	0x20	BUCK1 overcurrent event
EVENTS_BUCK2OC	0x21	BUCK2 overcurrent event
EVENTS_BUCK3OC	0x22	BUCK3 overcurrent event
INTEN0	0x2A	Enable or disable interrupts
INTENSET0	0x2B	Interrupt enable SET
INTENCLR0	0x2C	Interrupt enable CLEAR
INTPEND0	0x2D	Interrupt pending
BUCK0VOUTULP	0x3A	BUCK0 voltage setting (hysteretic mode)
BUCK0VOUTPWM	0x3B	BUCK0 voltage setting (PWM mode)
BUCK1VOUTULP	0x3C	BUCK1 voltage setting (hysteretic mode)
BUCK1VOUTPWM	0x3D	BUCK1 voltage setting (PWM mode)
BUCK2VOUTULP	0x40	BUCK2 voltage setting (hysteretic mode)
BUCK2VOUTPWM	0x41	BUCK2 voltage setting (PWM mode)
BUCK3SELDAC	0x44	Internal DAC enable for BUCK3
BUCK3VOUT	0x45	BUCK3 voltage setting
LDO0VOUT	0x46	LDO0 voltage setting
BUCK0CONFPWMMODE	0x4A	BUCK0 PWM mode configuration
BUCK1CONFPWMMODE	0x4B	BUCK1 PWM mode configuration
BUCK2CONFPWMMODE	0x4C	BUCK2 PWM mode configuration
BUCK3CONFPWMMODE	0x4D	BUCK3 PWM mode configuration
BUCKMODEPADCONF	0x4E	BUCK_MODE pin configuration
THDYNPOWERUP	0x50	Thermal sensors' dynamic configuration
PADDRIVESTRENGTH	0x53	Drive strength control
WDARMEDVALUE	0x54	Arm watchdog or wake-up timer. Use strobe WDARMEDSTROBE.
WDARMEDSTROBE	0x55	Strobe for register WDARMEDVALUE
WDTRIGGERVALUE0	0x56	Watchdog and wake-up timer trigger value, lowest byte. Use strobe WDDATASTROBE
WDTRIGGERVALUE1	0x57	Watchdog and wake-up timer trigger value, middle byte. Use strobe WDDATASTROBE
WDTRIGGERVALUE2	0x58	Watchdog and wake-up timer trigger value, highest byte. Use strobe WDDATASTROBE
WDDATASTROBE	0x5D	Strobe for registers WDTRIGGERVALUE
WDPWRUPVALUE	0x5E	Watchdog and wake-up timer enable. Use Strobe WDPWRUPSTROBE
WDPWRUPSTROBE	0x5F	Strobe for register WDPWRUPVALUE
WDKICK	0x60	Watchdog kick
WDREQPOWERDOWN	0x62	Enter hibernate mode
GPIOOUTSET	0x69	GPIO output value SET
GPIOOUTCLR	0x6A	GPIO output value CLEAR
GPIOIN	0x6B	GPIO input value
GPIO0CONF	0x6C	GPIO0 configuration
GPIO1CONF	0x6D	GPIO1 configuration
GPIO2CONF	0x6E	GPIO2 configuration
LDO0CTRL	0x71	LDO0 current limiter, output high-impedance and pulldown control
LDO1CTRL	0x73	LDO1 current limiter, output high-impedance and pulldown control
OVERRIDEPWRUPBUCK	0xAB	Override for disabling BUCK1 or/and BUCK2 regulators

SWREADY

Address offset: 0x01

Software ready


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	SWREADY			Before this bit is set, nPM6001 does not react to BUCK_MODEx pins.
			NOTREADY	0	Software configuration is not yet done. BUCKs are running in PWM mode.
			READY	1	Software configuration is ready. Pins BUCK_MODEx may be used to control BUCKs' PWM modes.

TASKS_START_BUCK3

Address offset: 0x02

Start BUCK3


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_START_BUCK3			Start BUCK3
			Trigger	1	Trigger task

TASKS_START_LDO0

Address offset: 0x03

Start LDO0


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_START_LDO0			Start LDO0
			Trigger	1	Trigger task

TASKS_START_LDO1

Address offset: 0x04

Start LDO1


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_START_LDO1			Start LDO1
			Trigger	1	Trigger task

TASKS_START_THWARN

Address offset: 0x06

Start thermal warning sensor


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_START_THWARN			Start thermal warning sensor
			Trigger	1	Trigger task

TASKS_START_TH_SHUTDN

Address offset: 0x07

Start thermal shutdown sensor


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_START_TH_SHUTDN			Start thermal shutdown sensor
			Trigger	1	Trigger task

TASKS_STOP_BUCK3

Address offset: 0x08

Stop BUCK3


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_STOP_BUCK3			Stop BUCK3
			Trigger	1	Trigger task

TASKS_STOP_LDO0

Address offset: 0x09

Stop LDO0


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_STOP_LDO0			Stop LDO0
			Trigger	1	Trigger task

TASKS_STOP_LDO1

Address offset: 0x0A

Stop LDO1


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_STOP_LDO1			Stop LDO1
			Trigger	1	Trigger task

TASKS_STOP_THWARN

Address offset: 0x0C

Stop thermal warning sensor


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_STOP_THWARN			Stop thermal warning sensor
			Trigger	1	Trigger task

TASKS_STOP_THSHUTDN

Address offset: 0x0D

Stop thermal shutdown sensor


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_STOP_THSHUTDN			Stop thermal shutdown sensor
			Trigger	1	Trigger task

TASKS_UPDATE_VOUTPWM

Address offset: 0x0E

Update output voltage settings for BUCK0, BUCK1 and BUCK2


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKS_UPDATE_VOUTPWM			Update output voltage settings for BUCK0, BUCK1 and BUCK2
			Trigger	1	Trigger task

EVENTS_THWARN

Address offset: 0x1E

Thermal warning event


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	EVENTS_THWARN			Thermal warning event
			NotGenerated	0	Event not generated
			Generated	1	Event generated

EVENTS_BUCK0OC

Address offset: 0x1F

BUCK0 overcurrent event


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	EVENTS_BUCK0OC			BUCK0 overcurrent event
			NotGenerated	0	Event not generated
			Generated	1	Event generated

EVENTS_BUCK1OC

Address offset: 0x20

BUCK1 overcurrent event


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	EVENTS_BUCK1OC			BUCK1 overcurrent event
			NotGenerated	0	Event not generated
			Generated	1	Event generated

EVENTS_BUCK2OC

Address offset: 0x21

BUCK2 overcurrent event


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	EVENTS_BUCK2OC			BUCK2 overcurrent event
			NotGenerated	0	Event not generated
			Generated	1	Event generated

EVENTS_BUCK3OC

Address offset: 0x22

BUCK3 overcurrent event


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	EVENTS_BUCK3OC			BUCK3 overcurrent event
			NotGenerated	0	Event not generated
			Generated	1	Event generated

INTEN0

Address offset: 0x2A

Enable or disable interrupts


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	RW	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.
C	RW	RESERVED2			Reserved2. Do not write '1' to bits marked as RESERVEDn.
D	RW	THWARN			Enable or disable interrupt for event thermal warning
			DISABLED	0	Disable
			ENABLED	1	Enable
E	RW	BUCK0OC			Enable or disable interrupt for event BUCK0 overcurrent
			DISABLED	0	Disable
			ENABLED	1	Enable
F	RW	BUCK1OC			Enable or disable interrupt for event BUCK1 overcurrent
			DISABLED	0	Disable
			ENABLED	1	Enable
G	RW	BUCK2OC			Enable or disable interrupt for event BUCK2 overcurrent
			DISABLED	0	Disable
			ENABLED	1	Enable
H	RW	BUCK3OC			Enable or disable interrupt for event BUCK3 overcurrent
			DISABLED	0	Disable
			ENABLED	1	Enable

INTENSET0

Address offset: 0x2B

Interrupt enable SET


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	RW W1S	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.
C	RW W1S	RESERVED2			Reserved2. Do not write '1' to bits marked as RESERVEDn.
D	RW W1S	THWARN			Thermal warning
			NOACTION	0	No Action
			SET	1	Set
E	RW W1S	BUCK0OC			BUCK0 overcurrent
			NOACTION	0	No Action
			SET	1	Set
F	RW W1S	BUCK1OC			BUCK1 overcurrent
			NOACTION	0	No Action
			SET	1	Set
G	RW W1S	BUCK2OC			BUCK2 overcurrent
			NOACTION	0	No Action
			SET	1	Set
H	RW W1S	BUCK3OC			BUCK3 overcurrent
			NOACTION	0	No Action
			SET	1	Set

INTENCLR0

Address offset: 0x2C

Interrupt enable CLEAR


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	RW W1C	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.
C	RW W1C	RESERVED2			Reserved2. Do not write '1' to bits marked as RESERVEDn.
D	RW W1C	THWARN			Thermal warning
			NOACTION	0	No Action
			CLEAR	1	Clear
E	RW W1C	BUCK0OC			BUCK0 overcurrent
			NOACTION	0	No Action
			CLEAR	1	Clear
F	RW W1C	BUCK1OC			BUCK1 overcurrent
			NOACTION	0	No Action
			CLEAR	1	Clear
G	RW W1C	BUCK2OC			BUCK2 overcurrent
			NOACTION	0	No Action
			CLEAR	1	Clear
H	RW W1C	BUCK3OC			BUCK3 overcurrent
			NOACTION	0	No Action
			CLEAR	1	Clear

INTPEND0

Address offset: 0x2D

Interrupt pending


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	R	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	R	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.
C	R	RESERVED2			Reserved2. Do not write '1' to bits marked as RESERVEDn.
D	R	THWARN			Thermal warning
			NOTPENDING	0	Not Pending
			PENDING	1	Pending
E	R	BUCK0OC			BUCK0 overcurrent
			NOTPENDING	0	Not Pending
			PENDING	1	Pending
F	R	BUCK1OC			BUCK1 overcurrent
			NOTPENDING	0	Not Pending
			PENDING	1	Pending
G	R	BUCK2OC			BUCK2 overcurrent
			NOTPENDING	0	Not Pending
			PENDING	1	Pending
H	R	BUCK3OC			BUCK3 overcurrent
			NOTPENDING	0	Not Pending
			PENDING	1	Pending

BUCK0VOUTULP

Address offset: 0x3A

BUCK0 voltage setting (hysteretic mode)


Bit number						7	6	5	4	3	2	1	0
ID									B	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK0 voltage setting for hysteretic mode. Setting must be identical with register BUCK0VOUTPWM.
			SET1V8	0	SET 1V8
			SET1V9	1	SET 1V9
			SET2V0	2	SET 2V0
			SET2V1	3	SET 2V1
			SET2V2	4	SET 2V2
			SET2V3	5	SET 2V3
			SET2V4	6	SET 2V4
			SET2V5	7	SET 2V5
			SET2V6	8	SET 2V6
			SET2V7	9	SET 2V7
			SET2V8	10	SET 2V8
			SET2V9	11	SET 2V9
			SET3V0	12	SET 3V0
			SET3V1	13	SET 3V1
			SET3V2	14	SET 3V2
			SET3V3	15	SET 3V3
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

BUCK0VOUTPWM

Address offset: 0x3B

BUCK0 voltage setting (PWM mode)


Bit number						7	6	5	4	3	2	1	0
ID									B	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK0 voltage setting for PWM mode. After updating this register, run TASK_UPDATE_VOUTPWM.
			SET1V8	0	SET 1V8
			SET1V9	1	SET 1V9
			SET2V0	2	SET 2V0
			SET2V1	3	SET 2V1
			SET2V2	4	SET 2V2
			SET2V3	5	SET 2V3
			SET2V4	6	SET 2V4
			SET2V5	7	SET 2V5
			SET2V6	8	SET 2V6
			SET2V7	9	SET 2V7
			SET2V8	10	SET 2V8
			SET2V9	11	SET 2V9
			SET3V0	12	SET 3V0
			SET3V1	13	SET 3V1
			SET3V2	14	SET 3V2
			SET3V3	15	SET 3V3
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

BUCK1VOUTULP

Address offset: 0x3C

BUCK1 voltage setting (hysteretic mode)


Bit number						7	6	5	4	3	2	1	0
ID									B	A	A	A	A
Reset 0x02						0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK1 voltage setting for hysteretic mode. Setting must be identical with register BUCK1VOUTPWM.
			SET0V70	0	SET 0V70
			SET0V75	1	SET 0V75
			SET0V80	2	SET 0V80
			SET0V85	3	SET 0V85
			SET0V90	4	SET 0V90
			SET0V95	5	SET 0V95
			SET1V00	6	SET 1V00
			SET1V05	7	SET 1V05
			SET1V10	8	SET 1V10
			SET1V15	9	SET 1V15
			SET1V20	10	SET 1V20
			SET1V25	11	SET 1V25
			SET1V30	12	SET 1V30
			SET1V35	13	SET 1V35
			SET1V40	14	SET 1V40
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

BUCK1VOUTPWM

Address offset: 0x3D

BUCK1 voltage setting (PWM mode)


Bit number						7	6	5	4	3	2	1	0
ID									B	A	A	A	A
Reset 0x02						0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK1 voltage setting for PWM mode. After updating this register, run TASK_UPDATE_VOUTPWM
			SET0V70	0	SET 0V70
			SET0V75	1	SET 0V75
			SET0V80	2	SET 0V80
			SET0V85	3	SET 0V85
			SET0V90	4	SET 0V90
			SET0V95	5	SET 0V95
			SET1V00	6	SET 1V00
			SET1V05	7	SET 1V05
			SET1V10	8	SET 1V10
			SET1V15	9	SET 1V15
			SET1V20	10	SET 1V20
			SET1V25	11	SET 1V25
			SET1V30	12	SET 1V30
			SET1V35	13	SET 1V35
			SET1V40	14	SET 1V40
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

BUCK2VOUTULP

Address offset: 0x40

BUCK2 voltage setting (hysteretic mode)


Bit number						7	6	5	4	3	2	1	0
ID									A	A	A	A	A
Reset 0x0A						0	0	0	0	1	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK2 voltage setting for hysteretic mode. Setting must be identical with register BUCK2VOUTPWM.
			SET1V20	10	SET 1V20
			SET1V25	11	SET 1V25
			SET1V30	12	SET 1V30
			SET1V35	13	SET 1V35
			SET1V40	14	SET 1V40

BUCK2VOUTPWM

Address offset: 0x41

BUCK2 voltage setting (PWM mode)


Bit number						7	6	5	4	3	2	1	0
ID									A	A	A	A	A
Reset 0x0A						0	0	0	0	1	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK2 voltage setting for PWM-mode. After updating this register, run TASK_UPDATE_VOUTPWM.
			SET1V20	10	SET 1V20
			SET1V25	11	SET 1V25
			SET1V30	12	SET 1V30
			SET1V35	13	SET 1V35
			SET1V40	14	SET 1V40

BUCK3SELDAC

Address offset: 0x44

Internal DAC enable for BUCK3


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	SELECT			BUCK3 internal DAC
			DISABLE	0	Disable
			ENABLE	1	Enable

BUCK3VOUT

Address offset: 0x45

BUCK3 voltage setting


Bit number						7	6	5	4	3	2	1	0
ID							A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			BUCK3 voltage setting
			SET0V5	0	SET 0V5
			SET0V525	1	SET 0V525
			SET0V55	2	SET 0V55
			SET0V575	3	SET 0V575
			SET0V6	4	SET 0V6
			SET0V625	5	SET 0V625
			SET0V65	6	SET 0V65
			SET0V675	7	SET 0V675
			SET0V7	8	SET 0V7
			SET0V725	9	SET 0V725
			SET0V75	10	SET 0V75
			SET0V775	11	SET 0V775
			SET0V8	12	SET 0V8
			SET0V825	13	SET 0V825
			SET0V85	14	SET 0V85
			SET0V875	15	SET 0V875
			SET0V9	16	SET 0V9
			SET0V925	17	SET 0V925
			SET0V95	18	SET 0V95
			SET0V975	19	SET 0V975
			SET1V0	20	SET 1V0
			SET1V025	21	SET 1V025
			SET1V05	22	SET 1V05
			SET1V075	23	SET 1V075
			SET1V1	24	SET 1V1
			SET1V125	25	SET 1V125
			SET1V15	26	SET 1V15
			SET1V175	27	SET 1V175
			SET1V2	28	SET 1V2
			SET1V225	29	SET 1V225
			SET1V25	30	SET 1V25
			SET1V275	31	SET 1V275
			SET1V3	32	SET 1V3
			SET1V325	33	SET 1V325
			SET1V35	34	SET 1V35
			SET1V375	35	SET 1V375
			SET1V4	36	SET 1V4
			SET1V425	37	SET 1V425
			SET1V45	38	SET 1V45
			SET1V475	39	SET 1V475
			SET1V5	40	SET 1V5
			SET1V525	41	SET 1V525
			SET1V55	42	SET 1V55
			SET1V575	43	SET 1V575
			SET1V6	44	SET 1V6
			SET1V625	45	SET 1V625
			SET1V65	46	SET 1V65
			SET1V675	47	SET 1V675
			SET1V7	48	SET 1V7
			SET1V725	49	SET 1V725
			SET1V75	50	SET 1V75
			SET1V775	51	SET 1V775
			SET1V8	52	SET 1V8
			SET1V825	53	SET 1V825
			SET1V85	54	SET 1V85
			SET1V875	55	SET 1V875
			SET1V9	56	SET 1V9
			SET1V925	57	SET 1V925
			SET1V95	58	SET 1V95
			SET1V975	59	SET 1V975
			SET2V0	60	SET 2V0
			SET2V025	61	SET 2V025
			SET2V05	62	SET 2V05
			SET2V075	63	SET 2V075
			SET2V1	64	SET 2V1
			SET2V125	65	SET 2V125
			SET2V15	66	SET 2V15
			SET2V175	67	SET 2V175
			SET2V2	68	SET 2V2
			SET2V225	69	SET 2V225
			SET2V25	70	SET 2V25
			SET2V275	71	SET 2V275
			SET2V3	72	SET 2V3
			SET2V325	73	SET 2V325
			SET2V35	74	SET 2V35
			SET2V375	75	SET 2V375
			SET2V4	76	SET 2V4
			SET2V425	77	SET 2V425
			SET2V45	78	SET 2V45
			SET2V475	79	SET 2V475
			SET2V5	80	SET 2V5
			SET2V525	81	SET 2V525
			SET2V55	82	SET 2V55
			SET2V575	83	SET 2V575
			SET2V6	84	SET 2V6
			SET2V625	85	SET 2V625
			SET2V65	86	SET 2V65
			SET2V675	87	SET 2V675
			SET2V7	88	SET 2V7
			SET2V725	89	SET 2V725
			SET2V75	90	SET 2V75
			SET2V775	91	SET 2V775
			SET2V8	92	SET 2V8
			SET2V825	93	SET 2V825
			SET2V85	94	SET 2V85
			SET2V875	95	SET 2V875
			SET2V9	96	SET 2V9
			SET2V925	97	SET 2V925
			SET2V95	98	SET 2V95
			SET2V975	99	SET 2V975
			SET3V0	100	SET 3V0
			SET3V025	101	SET 3V025
			SET3V05	102	SET 3V05
			SET3V075	103	SET 3V075
			SET3V1	104	SET 3V1
			SET3V125	105	SET 3V125
			SET3V15	106	SET 3V15
			SET3V175	107	SET 3V175
			SET3V2	108	SET 3V2
			SET3V225	109	SET 3V225
			SET3V25	110	SET 3V25
			SET3V275	111	SET 3V275
			SET3V3	112	SET 3V3

LDO0VOUT

Address offset: 0x46

LDO0 voltage setting


Bit number						7	6	5	4	3	2	1	0
ID								B	A	A	A	A	A
Reset 0x1A						0	0	0	1	1	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VOLTAGE			LDO0 voltage setting
			SET1V8	6	SET 1.8V
			SET2V1	11	SET 2.1V
			SET2V41	16	SET 2.41V
			SET2V7	21	SET 2.7V
			SET3V0	26	SET 3.0V
			SET3V3	30	SET 3.3V
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

BUCK0CONFPWMMODE

Address offset: 0x4A

BUCK0 PWM mode configuration


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x03						0	0	0	0	0	0	1	1
ID	R/W	Field	Value ID	Value	Description
A	RW	PADBUCKMODE0			Configure pin BUCK_MODE0 for BUCK0
			NOPWM	0	BUCK0 is not set to PWM mode when pin BUCK_MODE0 is high
			PWM	1	BUCK0 is set to PWM mode when pin BUCK_MODE0 is high
B	RW	PADBUCKMODE1			Configure pin BUCK_MODE1 for BUCK0
			NOPWM	0	BUCK0 is not set to PWM mode when pin BUCK_MODE1 is high
			PWM	1	BUCK0 is set to PWM mode when pin BUCK_MODE1 is high
C	RW	PADBUCKMODE2			Configure pin BUCK_MODE2 for BUCK0
			NOPWM	0	BUCK0 is not set to PWM mode when pin BUCK_MODE2 is high
			PWM	1	BUCK0 is set to PWM mode when pin BUCK_MODE2 is high
D	RW	SETFORCEPWM			Set BUCK0 to PWM mode
			OFF	0	BUCK0 PWM mode is controlled by BUCK_MODE pins
			ON	1	BUCK0 is set to PWM mode regardless of BUCK_MODE pin states

BUCK1CONFPWMMODE

Address offset: 0x4B

BUCK1 PWM mode configuration


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x02						0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	PADBUCKMODE0			Configure pin BUCK_MODE0 for BUCK1
			NOPWM	0	BUCK1 is not set to PWM mode when pin BUCK_MODE0 is high
			PWM	1	BUCK1 is set to PWM mode when pin BUCK_MODE0 is high
B	RW	PADBUCKMODE1			Configure pin BUCK_MODE1 for BUCK1
			NOPWM	0	BUCK1 is not set to PWM mode when pin BUCK_MODE1 is high
			PWM	1	BUCK1 is set to PWM mode when pin BUCK_MODE1 is high
C	RW	PADBUCKMODE2			Configure pin BUCK_MODE2 for BUCK1
			NOPWM	0	BUCK1 is not set to PWM mode when pin BUCK_MODE2 is high
			PWM	1	BUCK1 is set to PWM mode when pin BUCK_MODE2 is high
D	RW	SETFORCEPWM			Set BUCK1 to PWM mode
			OFF	0	BUCK1 PWM mode is controlled by BUCK_MODE pins
			ON	1	BUCK1 is set to PWM mode regardless of BUCK_MODE pin states

BUCK2CONFPWMMODE

Address offset: 0x4C

BUCK2 PWM mode configuration


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x02						0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value	Description
A	RW	PADBUCKMODE0			Configure pin BUCK_MODE0 for BUCK2
			NOPWM	0	BUCK2 is not set to PWM mode when pin BUCK_MODE0 is high
			PWM	1	BUCK2 set to PWM mode when pin BUCK_MODE0 is high
B	RW	PADBUCKMODE1			Configure pin BUCK_MODE1 for BUCK2
			NOPWM	0	BUCK2 is not set to PWM mode when pin BUCK_MODE1 is high
			PWM	1	BUCK2 is set to PWM mode when pin BUCK_MODE1 is high
C	RW	PADBUCKMODE2			Configure pin BUCK_MODE2 for BUCK2
			NOPWM	0	BUCK2 is not set to PWM mode when pin BUCK_MODE2 is high
			PWM	1	BUCK2 is set to PWM mode when pin BUCK_MODE2 is high
D	RW	SETFORCEPWM			Set BUCK2 to PWM mode
			OFF	0	BUCK2 PWM mode is controlled by BUCK_MODE pins
			ON	1	BUCK2 is set to PWM mode regardless of BUCK_MODE pin states

BUCK3CONFPWMMODE

Address offset: 0x4D

BUCK3 PWM mode configuration


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x04						0	0	0	0	0	1	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	PADBUCKMODE0			Configure pin BUCK_MODE0 for BUCK3
			NOPWM	0	BUCK3 is not set to PWM mode when pin BUCK_MODE0 is high
			PWM	1	BUCK3 is set to PWM mode when pin BUCK_MODE0 is high
B	RW	PADBUCKMODE1			Configure pin BUCK_MODE1 for BUCK3
			NOPWM	0	BUCK3 is not set to PWM mode when pin BUCK_MODE1 is high
			PWM	1	BUCK3 is set to PWM mode when pin BUCK_MODE1 is high
C	RW	PADBUCKMODE2			Configure pin BUCK_MODE2 for BUCK3
			NOPWM	0	BUCK3 is not set to PWM mode when pin BUCK_MODE2 is high
			PWM	1	BUCK3 is set to PWM mode when pin BUCK_MODE2 is high
D	RW	SETFORCEPWM			Set BUCK3 to PWM mode
			OFF	0	BUCK3 PWM mode is controlled by BUCK_MODE pins
			ON	1	BUCK3 is set to PWM mode regardless of BUCK_MODE pin states

BUCKMODEPADCONF

Address offset: 0x4E

BUCK_MODE pin configuration


Bit number						7	6	5	4	3	2	1	0
ID							F	E	D		C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	BUCKMODE0PADTYPE			BUCK_MODE0 input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
B	RW	BUCKMODE1PADTYPE			BUCK_MODE1 input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
C	RW	BUCKMODE2PADTYPE			BUCK_MODE2 input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
D	RW	BUCKMODE0PULLD			BUCK_MODE0 pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
E	RW	BUCKMODE1PULLD			BUCK_MODE1 pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
F	RW	BUCKMODE2PULLD			BUCK_MODE2 pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled

THDYNPOWERUP

Address offset: 0x50

Thermal sensors' dynamic configuration


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	BUCK0PWM			BUCK0 PWM mode controls thermal sensor
			NOEFFECT	0	Thermal sensor is not enabled while BUCK0 is in PWM mode
			PWRUP	1	Thermal sensor is enabled while BUCK0 is in PWM mode
B	RW	BUCK1PWM			BUCK1 PWM mode controls thermal sensor
			NOEFFECT	0	Thermal sensor is not enabled while BUCK1 is in PWM mode
			PWRUP	1	Thermal sensor is enabled while BUCK1 is in PWM mode
C	RW	BUCK2PWM			BUCK2 PWM mode controls thermal sensor
			NOEFFECT	0	Thermal sensor is not enabled while BUCK2 is in PWM mode
			PWRUP	1	Thermal sensor is enabled while BUCK2 is in PWM mode
D	RW	BUCK3PWM			BUCK3 PWM mode controls thermal sensor
			NOEFFECT	0	Thermal sensor is not enabled while BUCK3 is in PWM mode
			PWRUP	1	Thermal sensor is enabled while BUCK3 is in PWM mode
E	RW	WARNING			Thermal warning sensor
			NOTSELECTED	0	Thermal warning sensor is not enabled dynamically
			SELECTED	1	Thermal warning sensor is enabled dynamically
F	RW	SHUTDWN			Thermal shutdown sensor
			NOTSELECTED	0	Thermal shutdown sensor is not enabled dynamically
			SELECTED	1	Thermal shutdown sensor is enabled dynamically

PADDRIVESTRENGTH

Address offset: 0x53

Drive strength control


Bit number						7	6	5	4	3	2	1	0
ID							G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	RW	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.
C	RW	READY			Drive strength for pin READY
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
D	RW	NINT			Drive strength for pin nINT
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
E	RW	RESERVED2			Reserved2. Do not write '1' to bits marked as RESERVEDn.
F	RW	SDA			Drive strength for pin SDA
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
G	RW	RESERVED3			Reserved3. Do not write '1' to bits marked as RESERVEDn.

WDARMEDVALUE

Address offset: 0x54

Arm watchdog or wake-up timer. Use strobe WDARMEDSTROBE.


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VALUE			Arm or disarm watchdog or wake-up timer
			DISABLE	0	Disarmed
			ENABLE	1	Armed

WDARMEDSTROBE

Address offset: 0x55

Strobe for register WDARMEDVALUE


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	STROBE			Strobe for register WDARMEDVALUE
			NOEFFECT	0	No effect
			STROBE	1	Strobe

WDTRIGGERVALUE0

Address offset: 0x56

Watchdog and wake-up timer trigger value, lowest byte. Use strobe WDDATASTROBE


Bit number						7	6	5	4	3	2	1	0
ID						A	A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VALUE0			Watchdog and wakeup timer trigger value is a 24-bit value programmed into three registers. This is the lowest byte. Lsb equals to 4 s. Do not use values 0 and 1.
			SEL0	0	Sel0
			SEL2	2	Sel2
			SEL3	3	Sel3
			SEL4	4	Sel4
			SEL5	5	Sel5
			SEL6	6	Sel6
			SEL7	7	Sel7
			SEL8	8	Sel8
			SEL16	16	Sel16
			SEL32	32	Sel32
			SEL64	64	Sel64
			SEL128	128	Sel128

WDTRIGGERVALUE1

Address offset: 0x57

Watchdog and wake-up timer trigger value, middle byte. Use strobe WDDATASTROBE


Bit number						7	6	5	4	3	2	1	0
ID						A	A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VALUE1			Watchdog and wakeup timer trigger value, middle byte.
			SEL0	0	Sel0
			SEL1	1	Sel1
			SEL2	2	Sel2
			SEL4	4	Sel4
			SEL8	8	Sel8
			SEL16	16	Sel16
			SEL32	32	Sel32
			SEL64	64	Sel64
			SEL128	128	Sel128

WDTRIGGERVALUE2

Address offset: 0x58

Watchdog and wake-up timer trigger value, highest byte. Use strobe WDDATASTROBE


Bit number						7	6	5	4	3	2	1	0
ID						A	A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	VALUE2			Watchdog and wakeup timer trigger value, highest byte.
			SEL0	0	Sel0
			SEL1	1	Sel1
			SEL2	2	Sel2
			SEL4	4	Sel4
			SEL8	8	Sel8
			SEL16	16	Sel16
			SEL32	32	Sel32
			SEL64	64	Sel64
			SEL128	128	Sel128

WDDATASTROBE

Address offset: 0x5D

Strobe for registers WDTRIGGERVALUE


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	STROBE			Strobe for registers WDTRIGGERVALUEx
			NOEFFECT	0	No effect
			STROBE	1	Strobe

WDPWRUPVALUE

Address offset: 0x5E

Watchdog and wake-up timer enable. Use Strobe WDPWRUPSTROBE


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	OSC			Oscillator enable for watchdog and wake-up timer
			DISABLE	0	Disable
			ENABLE	1	Enable
B	RW	COUNTER			Counter enable for watchdog and wake-up timer
			DISABLE	0	Disable
			ENABLE	1	Enable
C	RW	LS			Clock levelshifter enable for watchdog and wake-up timer
			DISABLE	0	Disable
			ENABLE	1	Enable

WDPWRUPSTROBE

Address offset: 0x5F

Strobe for register WDPWRUPVALUE


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	STROBE			Strobe for register WDPWRUPVALUE
			NOEFFECT	0	No effect
			STROBE	1	Strobe

WDKICK

Address offset: 0x60

Watchdog kick


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	KICK			Watchdog counter reset
			NOEFFECT	0	No effect
			KICK	1	Reset counter

WDREQPOWERDOWN

Address offset: 0x62

Enter hibernate mode


Bit number						7	6	5	4	3	2	1	0
ID												B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	HARDPOWERDOWN			Enter hibernate mode
			NOREQUEST	0	No effect
			REQUEST	1	Enter hibernate mode
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

GPIOOUTSET

Address offset: 0x69

GPIO output value SET


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	GPIO0OUTSET			Set GPIO0
			NOEFFECT	0	No effect
			SET	1	Set output high
B	RW W1S	GPIO1OUTSET			Set GPIO1
			NOEFFECT	0	No effect
			SET	1	Set output high
C	RW W1S	GPIO2OUTSET			Set GPIO2
			NOEFFECT	0	No effect
			SET	1	Set output high

GPIOOUTCLR

Address offset: 0x6A

GPIO output value CLEAR


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	GPIO0OUTCLR			Clear GPIO0
			NOEFFECT	0	No effect
			CLR	1	Set output low
B	RW W1C	GPIO1OUTCLR			Clear GPIO1
			NOEFFECT	0	No effect
			CLR	1	Set output low
C	RW W1C	GPIO2OUTCLR			Clear GPIO2
			NOEFFECT	0	No effect
			CLR	1	Set output low

GPIOIN

Address offset: 0x6B

GPIO input value


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	R	GPIO0IN			GPIO0 input value
			LOW	0	Input is low
			HIGH	1	Input is high
B	R	GPIO1IN			GPIO1 input value
			LOW	0	Input is low
			HIGH	1	Input is high
C	R	GPIO2IN			GPIO2 input value
			LOW	0	Input is low
			HIGH	1	Input is high

GPIO0CONF

Address offset: 0x6C

GPIO0 configuration


Bit number						7	6	5	4	3	2	1	0
ID						F	E	D			C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	DIRECTION			Direction
			INPUT	0	Input
			OUTPUT	1	Output
B	RW	INPUT			Input buffer
			DISABLED	0	Input disabled. Input value is 0.
			ENABLED	1	Input enabled
C	RW	PULLDOWN			Pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	DRIVE			Drive strength
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
E	RW	SENSE			Input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
F	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

GPIO1CONF

Address offset: 0x6D

GPIO1 configuration


Bit number						7	6	5	4	3	2	1	0
ID						F	E	D			C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	DIRECTION			Direction
			INPUT	0	Input
			OUTPUT	1	Output
B	RW	INPUT			Input buffer
			DISABLED	0	Input disabled. Input data is 0.
			ENABLED	1	Input enabled
C	RW	PULLDOWN			Pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	DRIVE			Drive strength
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
E	RW	SENSE			Input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
F	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

GPIO2CONF

Address offset: 0x6E

GPIO2 configuration


Bit number						7	6	5	4	3	2	1	0
ID						F	E	D			C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	DIRECTION			Direction
			INPUT	0	Input
			OUTPUT	1	Output
B	RW	INPUT			Input buffer
			DISABLED	0	Input disabled. Input data is 0.
			ENABLED	1	Input enabled
C	RW	PULLDOWN			Pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	DRIVE			Drive strength
			NORMAL	0	Normal drive strength
			HIGH	1	High drive strength
E	RW	SENSE			Input type
			SCHMITT	0	Schmitt trigger input
			CMOS	1	CMOS input
F	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.

LDO0CTRL

Address offset: 0x71

LDO0 current limiter, output high-impedance and pulldown control


Bit number						7	6	5	4	3	2	1	0
ID								E	D	C	B	A	A
Reset 0x10						0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	ILIMITVALUE			Current limiter level
			50MA	0	50 mA
			100MA	1	100 mA
			150MA	2	150 mA
			UNLIMITED	3	Unlimited
B	RW	HIGHZ			Output high impedance
			DISABLED	0	Disabled
			ENABLED	1	Enabled
C	RW	PULLDOWN			Output pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	ENAILIMITAFTERSTART			Current limiter after LDO start
			OFF	0	Off
			ON	1	On
E	RW	ENAILIMITDURINGSTART			Current limiter during LDO start
			OFF	0	Off
			ON	1	On

LDO1CTRL

Address offset: 0x73

LDO1 current limiter, output high-impedance and pulldown control


Bit number						7	6	5	4	3	2	1	0
ID							G	F	E	D	C	B	A
Reset 0x10						0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	ILIMITVALUE			Current limiter level
			150MA	0	150mA
			UNLIMITED	1	Unlimited
B	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
C	RW	HIGHZ			Output high impedance
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	PULLDOWN			Output pulldown
			DISABLED	0	Disabled
			ENABLED	1	Enabled
E	RW	ENAILIMITAFTERSTART			Current limiter after LDO start
			OFF	0	Off
			ON	1	On
F	RW	ENAILIMITDURINGSTART			Current limiter during LDO start
			OFF	0	Off
			ON	1	On
G	RW	RESERVED1			Reserved1. Do not write '1' to bits marked as RESERVEDn.

OVERRIDEPWRUPBUCK

Address offset: 0xAB

Override for disabling BUCK1 or/and BUCK2 regulators


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	RESERVED0			Reserved0. Do not write '1' to bits marked as RESERVEDn.
B	RW	BUCK1PWRUPOVERRIDE			BUCK1 power up override
			DISABLED	0	Disabled
			ENABLED	1	Enabled
C	RW	BUCK2PWRUPOVERRIDE			BUCK2 power up override
			DISABLED	0	Disabled
			ENABLED	1	Enabled
D	RW	SPARE0			Spare0
E	RW	RESERVED1			Reserved1.Do not write '1' to bits marked as RESERVEDn.
F	RW	BUCK1PWRUPOVERRIDEVALUE			BUCK1 power up override setting
			DISABLED	0	Disable BUCK1
			NOEFFECT	1	No effect
G	RW	BUCK2PWRUPOVERRIDEVALUE			BUCK2 power up override setting
			DISABLED	0	Disable BUCK2
			NOEFFECT	1	No effect
H	RW	SPARE1			Spare1