Reference circuitry

Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from www.nordicsemi.com.

The following reference circuits for nPM6001 show the schematics and components to support different configurations in a design.

Table 1. PCB application configuration
	Configuration 1	Configuration 2	Configuration 3
Description	Default configuration All power regulators in use	Normal configuration Only BUCK1 and LDO0 in use	Minimal configuration Only BUCK0 in use
BUCK0	Configured	Configured	Configured
BUCK1	Configured	Configured	Not used Connect VO1 to VIN
BUCK2	Configured	Not used Connect VO2 to VO0	Not used Connect VO2 to VO0
BUCK3	Configured	Not used	Not used
LDO0	Configured	Configured	Not used
LDO1	Configured	Not used	Not used

Configuration 1

The reference schematic and bill of materials for the default configuration are shown here.

Figure 1. Reference application schematics, configuration 1

In this configuration, the ENABLE pin is connected to VIN. When the input voltage rises above VIN_{VTH1_RISE}, the buck regulators start up in the following order:

BUCK0 with 1.8 V output voltage
BUCK1 with 0.8 V output voltage
BUCK2 with 1.2 V output voltage

BUCK[0..2] regulators start in PWM mode to ensure that the application system has enough power to start up. Once buck regulators are running, the READY pin is set.

The device can also be started with the ENABLE input pin. In this configuration, the ENABLE pin is disconnected from VIN and controlled by a circuitry that pulls ENABLE to VIN or ground level. Rising edge of the ENABLE triggers startup sequence if VIN is within specified range.

Table 2. Bill of material for configuration 1
Designator	Value	Description	Footprint
C1, C2, C3, C4, C13, C15, C17	1 µF	Capacitor, X5R, ±10 %, 10 V	0201
C5, C6, C7, C8, C9, C10, C11, C14, C16	10 µF	Capacitor, X7T, ±20 %, 10 V	0603
C12	4.7 µF	Capacitor, X7T, ±20 %, 10 V	0603
L1, L2, L3	2.2 µH	Fixed inductor, I_sat > 2 A, DCR < 100 mΩ	0806
L4	470 nH	Fixed inductor, I_sat > 1.5 A, DCR < 100 mΩ	0603
R1, R2	10 kΩ	Resistor, ±5 %, value depends on TWI bus speed and parasitic load capacitance	0201
R3, R4	4.7 kΩ	Resistor, ±5 %, value depends on parasitic load capacitance	0201
U1	nPM6001-CAAA	Low-power and high efficiency PMIC	WLCSP-45

Configuration 2

The reference schematic and bill of materials for a custom configuration are shown here.

Figure 3. Reference application schematics, configuration 2

In this configuration, the unused regulators are unpopulated and must be connected as shown in the schematic. When BUCK2 is not populated, the VO2 pin must be connected to VO0 output for the device to operate.

The READY pin is set when BUCK1 starts. That means the start-up sequence does not wait for unpopulated BUCKs, but continues to the next enabled BUCK and sets the READY pin. To minimize power consumption, it is recommended to disable the core circuit of the unpopulated regulator BUCK2 by writing to register OVERRIDE.PWRUP.BUCK[2, 6] = [1, 0].

Table 3. Bill of material for configuration 2
Designator	Value	Description	Footprint
C1, C2, C3, C4, C13, C17	1 µF	Capacitor, X5R, ±10 %, 10 V	0201
C5, C6, C7, C8, C14	10 µF	Capacitor, X7T, ±20 %, 10 V	0603
L1, L2	2.2 µH	Fixed inductor, I_sat > 2 A, DCR < 100 mΩ	0806
R1, R2	10 kΩ	Resistor, ±5 %, value depends on TWI bus speed and parasitic load capacitance	0201
R3, R4	4.7 kΩ	Resistor, ±5 %, value depends on parasitic load capacitance	0201
U1	nPM6001-CAAA	Low-power and high efficiency PMIC	WLCSP-45

Electrical specification

The following table contains the Schmitt trigger mode electrical specifications for standard digital I/O driver cells used in GPIO and BUCK_MODE[n] pins in configuration 2, where VO2 is supplied from an external source instead of BUCK2.

Table 4. Config. 2 Schmitt trigger mode electrical specification
Symbol	Description	Min.	Typ.	Max.	Units
VT_POS	Positive going input voltage threshold (custom configuration VO2=1.8 V)	1.0		1.3	V
VT_NEG	Negative going input voltage threshold (custom configuration VO2=1.8 V)	0.6		0.7	V
D_VT	Hysteresis (VT_POS - VT_NEG) (custom configuration VO2=1.8 V)		0.5		V
VT_POS	Positive going input voltage threshold (custom configuration VO2=3.3 V)	1.7		2.1	V
VT_NEG	Negative going input voltage threshold (custom configuration VO2=3.3 V)	1		1.3	V
D_VT	Hysteresis (VT_POS - VT_NEG) (custom configuration VO2=3.3 V)		0.75		V

Configuration 3

The reference schematic and bill of materials for a custom configuration are shown here.

Figure 4. Reference application schematics, configuration 3

In this configuration, the unused regulators are unpopulated and must be connected as shown in the schematic. VO1 must be connected to VIN and VO2 must be connected to VO0 output for the device to operate.

The READY pin is set when BUCK0 starts. To minimize power consumption, it is recommended to disable all core circuits of the unpopulated regulators by writing the following registers:

Disable BUCK1 circuits – OVERRIDE.PWRUP.BUCK[1, 5] = [1, 0]
Disable BUCK2 circuits – OVERRIDE.PWRUP.BUCK[2, 6] = [1, 0]

Unpopulated BUCK3, LDO0, and LDO1 registers do not need configuration.

Table 5. Bill of material for configuration 3
Designator	Value	Description	Footprint
C1, C2, C3, C4	1 µF	Capacitor, X5R, ±10 %, 10 V	0201
C5, C6	10 µF	Capacitor, X7T, ±20 %, 10 V	0603
L1	2.2 µH	Fixed inductor, I_sat > 2 A, DCR < 100 mΩ	0806
R1, R2	10 kΩ	Resistor, ±5 %, value depends on TWI bus speed and parasitic load capacitance	0201
R3, R4	4.7 kΩ	Resistor, ±5 %, value depends on parasitic load capacitance	0201
U1	nPM6001-CAAA	Low-power and high efficiency PMIC	WLCSP-45

PCB guidelines

A well designed PCB is necessary to achieve good performance. A poor layout can lead to loss in performance or functionality.

To ensure functionality, it is essential to follow the schematics and layout references closely.

A multilayer board with a solid ground plane is recommended for optimal performance.

The DC supply voltage should be decoupled with high performance capacitors as close as possible to the supply pins. This is important for DC/DC regulator input capacitors in order to minimize DC/DC noise levels. See the reference schematics for recommended decoupling capacitor values.

Long power supply lines on the PCB should be avoided. All device grounds, VIN and VDD connections, and bypass capacitors must be connected as close as possible to the device.

PCB layout example

The PCB layout shown here is a reference layout for configuration 1.

For all available reference layouts, see the Reference Layout section on the Downloads tab for nPM6001 on www.nordicsemi.com.

Note: No components on the bottom layer.