CSP39 (CBAA) package pin assignments

nRF54LC10A Preliminary Datasheet

The CSP39 pin assignment figure and table describe the pinouts for this variant of the device.

Pins that can be used as clock signals are shown in as red in the figure. For more information about clock pins, see Clock pins.

Figure 3. CSP39 pin assignments, top view
CSP39 pin assignments, top view
Table 5. CSP39 pin assignments
Pin Clock pin Name Function Description Dedicated function
A1

 

DECRF

Power

Power supply decoupling

 

A2

 

XC1

Analog input

Connection for 32 MHz crystal

 

A3

 

XC2

Analog input

Connection for 32 MHz crystal

 

A4

 

P1.01

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

 

A5

 

P1.00

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

 

A6

 

P1.10

ASO[1]

TRACECLK

AIN5

Digital I/O

Digital I/O

Digital I/O

Analog input

General purpose IO

TAMPC active shield output

Trace clock

Analog input

 

TAMPC

Trace

 

B2

 

NC

 

No connect. Leave unconnected.

 

B4

Yes

P1.08

Digital I/O

Digital I/O

General purpose I/O

GRTC CLKOUTFAST

 

GRTC

B5

Yes

P1.03

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input

 

B6

Yes

P1.12

TRACEDATA[1]

AIN7

Digital I/O

Digital I/O

Analog input

General purpose IO

Trace data

Analog input

 

Trace

 

C1

 

ANT

RF

Single ended radio antenna connection

 

D3

 

VSS

Power

Ground

 

D4

Yes

P1.16

FLPR.0

QSPI.SCK

Digital I/O

Digital I/O

Digital I/O

General purpose IO

General purpose IO

QSPI SCK

 

FLPR

FLPR(QSPI)

D5

 

P1.02

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input

 

D6

 

P1.13

TRACEDATA[2]

XL1

Digital I/O

Digital I/O

Analog input

General purpose IO

Trace data

Connection for 32.768 kHz crystal

 

Trace

 

E1

 

VSS

Power

Ground

 

E2

 

nRESET

Reset

Pin reset with on-chip pull-up

 

E3

 

P1.18

FLPR.3

QSPI.D2

RADIO[0]

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose IO

General purpose IO

QSPI D2

RADIO DFEGPIO

 

FLPR

FLPR(QSPI)

RADIO

E4

Yes

P1.17

FLPR.1

QSPI.D0

Digital I/O

Digital I/O

Digital I/O

General purpose IO

General purpose IO

QSPI D0

 

FLPR

FLPR(QSPI)

E5

 

P1.05

ASO[0]

EXTREF

Digital I/O

Digital I/O

Analog input

General purpose IO

TAMPC active shield output

External reference

 

TAMPC

E6

 

P1.14

TRACEDATA[3]

XL2

Digital I/O

Digital I/O

Analog input

General purpose IO

Trace data

Connection for 32.768 kHz crystal

 

Trace

 

F1

 

VSS

Power

Ground

 

F2

 

SWDCLK

Debug

Serial wire clock. Input with on-chip pull-down.

 

F3

Yes

P1.20

FLPR.5

QSPI.CSN

RADIO[2]

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose IO

General purpose IO

QSPI CSN

RADIO DFEGPIO

 

FLPR

FLPR(QSPI)

RADIO

F4

Yes

P1.19

FLPR.2

QSPI.D1

RADIO[1]

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose IO

General purpose IO

QSPI D1

RADIO DFEGPIO

 

FLPR

FLPR(QSPI)

RADIO

F5

Yes

P1.04

Digital I/O

General purpose I/O

 

F6

Yes

P1.11

ASI[1]

TRACEDATA[0]

SWO

AIN6

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Analog input

General purpose IO

TAMPC active shield input

Trace data

Serial wire output (SWO)

Analog input

 

TAMPC

Trace

 

G1

 

DECB

Power

Power supply

 

G2

 

SWDIO

Debug

Serial wire data. Bidirectional with standard-drive and on-chip pull-up.

 

G3

Yes

P0.04

Digital I/O

Digital I/O

General purpose I/O

GRTC CLKOUT32K

 

GRTC

G4

Yes

P0.03

Digital I/O

Digital I/O

General purpose I/O

GRTC PWM

 

GRTC

G5

 

P1.07

AIN4

ASI[0]

Digital I/O

Analog input

Digital I/O

General purpose IO

Analog input

TAMPC active shield input

 

TAMPC

G6

 

DECA

Power

Power supply decoupling

 

H1

 

VDD

Power

Power supply

 

H2

 

VSS

Power

Ground

 

H3

 

VDD

Power

Power supply

 

H4

 

VSS

Power

Ground

 

H5

 

DCC

Power

DC/DC converter output

 

H6

 

DECD

Power

Power supply decoupling