The CPU is able to read internal cache memories and tags for debug purposes.
The content of data and tag RAM's are accessible through registers SET[n].WAY[o].INFO (n=0..127) (o=0..1) and SET[n].WAY[o].DU[p].DATA[q] (n=0..127) (o=0..1) (p=0..3) (q=0..1).
Debug access is prevented by using register DEBUGLOCK.