Event, interrupt and revision registers

This section details the event, interrupt and device revision related registers.

Device revision

The revision information is available in registers REVISIONMSB and REVISIONLSB. See nPM1304 Compatibility Matrix for details.

Registers

Instances


Instance	Base address	Description
MAIN	0x00000000	MAIN registers MAIN Register map

Register overview


Register	Offset	Description
TASKSWRESET	0x1	Task force a full reboot power-cycle
EVENTSADCSET	0x2	ADC Event Set
EVENTSADCCLR	0x3	ADC Event Clear
INTENEVENTSADCSET	0x4	ADC Interrupt Enable Set
INTENEVENTSADCCLR	0x5	ADC Interrupt Enable Clear
EVENTSBCHARGER0SET	0x6	Battery temperature region and die temperature Event Set
EVENTSBCHARGER0CLR	0x7	Battery temperature region and die temperature Event Clear
INTENEVENTSBCHARGER0SET	0x8	Battery temperature region and die temperature Interrupt Enable Set
INTENEVENTSBCHARGER0CLR	0x9	Battery temperature region and die temperature Interrupt Enable Clear
EVENTSBCHARGER1SET	0xA	Charger Event Set
EVENTSBCHARGER1CLR	0xB	Charger Event Clear
INTENEVENTSBCHARGER1SET	0xC	Charger Interrupt Enable Set
INTENEVENTSBCHARGER1CLR	0xD	Charger Interrupt Enable Clear
EVENTSBCHARGER2SET	0xE	Battery Event Set
EVENTSBCHARGER2CLR	0xF	Battery Event Clear
INTENEVENTSBCHARGER2SET	0x10	Battery Interrupt Enable Set
INTENEVENTSBCHARGER2CLR	0x11	Battery Interrupt Enable Clear
EVENTSSHPHLDSET	0x12	SHPHLD pin and watchdog Event Set
EVENTSSHPHLDCLR	0x13	SHPHLD pin and watchdog Event Clear
INTENEVENTSSHPHLDSET	0x14	SHPHLD pin and watchdog Interrupt Enable Set
INTENEVENTSSHPHLDCLR	0x15	SHPHLD pin and watchdog Interrupt Enable Clear
EVENTSVBUSIN0SET	0x16	VBUS Event Set
EVENTSVBUSIN0CLR	0x17	VBUS Event Clear
INTENEVENTSVBUSIN0SET	0x18	VBUS Interrupt Enable Set
INTENEVENTSVBUSIN0CLR	0x19	VBUS Interrupt Enable Clear
EVENTSVBUSIN1SET	0x1A	Thermal and charger detection Event Set
EVENTSVBUSIN1CLR	0x1B	Thermal and charger detection Event Clear
INTENEVENTSVBUSIN1SET	0x1C	Thermal and charger detection Interrupt Enable Set
INTENEVENTSVBUSIN1CLR	0x1D	Thermal and charger detection Interrupt Enable Clear
EVENTSGPIOSET	0x22	GPIO Event Set
EVENTSGPIOCLR	0x23	GPIO Event Clear
INTENEVENTSGPIOSET	0x24	GPIO Interrupt Enable Set
INTENEVENTSGPIOCLR	0x25	GPIO Interrupt Enable Clear
REVISIONMSB	0x26	Revision MSB. See nPM1304 Compatibility Matrix for details.
REVISIONLSB	0x27	Revision LSB. See nPM1304 Compatibility Matrix for details.

TASKSWRESET

Address offset: 0x1

Task force a full reboot power-cycle


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKSWRESET			Turn off all supplies and apply internal reset
			NOEFFECT	0	No effect
			TRIGGER	1	Trigger task

EVENTSADCSET

Address offset: 0x2

ADC Event Set


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTADCVBATRDY			VBAT measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTADCNTCRDY			Battery NTC measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTADCTEMPRDY			Internal die temperature measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTADCVSYSRDY			VSYS voltage measurement measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTADCVSET1RDY			VSET1 pin measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTADCVSET2RDY			VSET2 pin measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
G	RW W1S	EVENTADCIBATRDY			IBAT measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
H	RW W1S	EVENTADCVBUS7V0RDY			VBUS measurement finished. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSADCCLR

Address offset: 0x3

ADC Event Clear


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTADCVBATRDY			VBAT measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTADCNTCRDY			Battery NTC measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTADCTEMPRDY			Internal die temperature measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTADCVSYSRDY			VSYS voltage measurement measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTADCVSET1RDY			VSET1 pin measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTADCVSET2RDY			VSET2 pin measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
G	RW W1C	EVENTADCIBATRDY			IBAT measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
H	RW W1C	EVENTADCVBUS7V0RDY			VBUS measurement finished. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSADCSET

Address offset: 0x4

ADC Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTADCVBATRDY			Writing 1 enables interrupts from EVENTADCVBATRDY
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTADCNTCRDY			Writing 1 enables interrupts from EVENTADCNTCRDY
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTADCTEMPRDY			Writing 1 enables interrupts from EVENTADCTEMPRDY
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTADCVSYSRDY			Writing 1 enables interrupts from EVENTADCVSYSRDY
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTADCVSET1RDY			Writing 1 enables interrupts from EVENTADCVSET1RDY
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTADCVSET2RDY			Writing 1 enables interrupts from EVENTADCVSET2RDY
			LOW	0	Low
			HIGH	1	High
G	RW W1S	EVENTADCIBATRDY			Writing 1 enables interrupts from EVENTADCIBATRDY
			LOW	0	Low
			HIGH	1	High
H	RW W1S	EVENTADCVBUS7V0RDY			Writing 1 enables interrupts from EVENTADCVBUS7V0RDY
			LOW	0	Low
			HIGH	1	High

INTENEVENTSADCCLR

Address offset: 0x5

ADC Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID						H	G	F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTADCVBATRDY			Writing 1 disables interrupts from EVENTADCVBATRDY
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTADCNTCRDY			Writing 1 disables interrupts from EVENTADCNTCRDY
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTADCTEMPRDY			Writing 1 disables interrupts from EVENTADCTEMPRDY
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTADCVSYSRDY			Writing 1 disables interrupts from EVENTADCVSYSRDY
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTADCVSET1RDY			Writing 1 disables interrupts from EVENTADCVSET1RDY
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTADCVSET2RDY			Writing 1 disables interrupts from EVENTADCVSET2RDY
			LOW	0	Low
			HIGH	1	High
G	RW W1C	EVENTADCIBATRDY			Writing 1 disables interrupts from EVENTADCIBATRDY
			LOW	0	Low
			HIGH	1	High
H	RW W1C	EVENTADCVBUS7V0RDY			Writing 1 disables interrupts from EVENTADCVBUS7V0RDY
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER0SET

Address offset: 0x6

Battery temperature region and die temperature Event Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTNTCCOLD			Battery temperature in cold region. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTNTCCOOL			Battery temperature in cool region. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTNTCWARM			Battery temperature in warm region. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTNTCHOT			Battery temperature in hot region. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTDIETEMPHIGH			Die temperature is over TCHGSTOP. Charging stops. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTDIETEMPRESUME			Die temperature is under TCHGRESUME. Charging resumes. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER0CLR

Address offset: 0x7

Battery temperature region and die temperature Event Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTNTCCOLD			Battery temperature in cold region. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTNTCCOOL			Battery temperature in cool region. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTNTCWARM			Battery temperature in warm region. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTNTCHOT			Battery temperature in hot region. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTDIETEMPHIGH			Die temperature is over TCHGSTOP. Charging stops. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTDIETEMPRESUME			Die temperature is under TCHGRESUME. Charging resumes. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER0SET

Address offset: 0x8

Battery temperature region and die temperature Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTNTCCOLD			Writing 1 enables interrupts from EVENTNTCCOLD
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTNTCCOOL			Writing 1 enables interrupts from EVENTNTCCOOL
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTNTCWARM			Writing 1 enables interrupts from EVENTNTCWARM
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTNTCHOT			Writing 1 enables interrupts from EVENTNTCHOT
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTDIETEMPHIGH			Writing 1 enables interrupts from EVENTDIETEMPHIGH
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTDIETEMPRESUME			Writing 1 enables interrupts from EVENTDIETEMPRESUME
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER0CLR

Address offset: 0x9

Battery temperature region and die temperature Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTNTCCOLD			Writing 1 disables interrupts from EVENTNTCCOLD
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTNTCCOOL			Writing 1 disables interrupts from EVENTNTCCOOL
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTNTCWARM			Writing 1 disables interrupts from EVENTNTCWARM
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTNTCHOT			Writing 1 disables interrupts from EVENTNTCHOT
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTDIETEMPHIGH			Writing 1 disables interrupts from EVENTDIETEMPHIGH
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTDIETEMPRESUME			Writing 1 disables interrupts from EVENTDIETEMPRESUME
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER1SET

Address offset: 0xA

Charger Event Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTSUPPLEMENT			Supplement mode activated. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTCHGTRICKLE			Tickle charge started. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTCHGCC			Constant current charging started. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTCHGCV			Constant voltage charging started. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTCHGCOMPLETED			Charging completed (battery full). Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTCHGERROR			Charging error. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER1CLR

Address offset: 0xB

Charger Event Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTSUPPLEMENT			Supplement mode activated. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTCHGTRICKLE			Tickle charge started. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTCHGCC			Constant current charging started. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTCHGCV			Constant voltage charging started. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTCHGCOMPLETED			Charging completed (battery full). Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTCHGERROR			Charging error. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER1SET

Address offset: 0xC

Charger Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTSUPPLEMENT			Writing 1 enables interrupts from EVENTSUPPLEMENT
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTCHGTRICKLE			Writing 1 enables interrupts from EVENTCHGTRICKLE
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTCHGCC			Writing 1 enables interrupts from EVENTCHGCC
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTCHGCV			Writing 1 enables interrupts from EVENTCHGCV
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTCHGCOMPLETED			Writing 1 enables interrupts from EVENTCHGCOMPLETED
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTCHGERROR			Writing 1 enables interrupts from EVENTCHGERROR
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER1CLR

Address offset: 0xD

Charger Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTSUPPLEMENT			Writing 1 disables interrupts from EVENTSUPPLEMENT
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTCHGTRICKLE			Writing 1 disables interrupts from EVENTCHGTRICKLE
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTCHGCC			Writing 1 disables interrupts from EVENTCHGCC
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTCHGCV			Writing 1 disables interrupts from EVENTCHGCV
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTCHGCOMPLETED			Writing 1 disables interrupts from EVENTCHGCOMPLETED
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTCHGERROR			Writing 1 disables interrupts from EVENTCHGERROR
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER2SET

Address offset: 0xE

Battery Event Set


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTBATDETECTED			Reserved (Battery detected.) Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTBATLOST			Battery lost. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTBATRECHARGE			Battery re-charge needed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSBCHARGER2CLR

Address offset: 0xF

Battery Event Clear


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTBATDETECTED			Reserved (Battery detected.) Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTBATLOST			Battery lost. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTBATRECHARGE			Battery re-charge needed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER2SET

Address offset: 0x10

Battery Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTBATDETECTED			Reserved (Writing 1 enables interrupts from EVENTBATDETECTED)
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTBATLOST			Reserved (Writing 1 enables interrupts from EVENTBATLOST)
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTBATRECHARGE			Writing 1 enables interrupts from EVENTBATRECHARGE
			LOW	0	Low
			HIGH	1	High

INTENEVENTSBCHARGER2CLR

Address offset: 0x11

Battery Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID											C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTBATDETECTED			Reserved (Writing 1 disables interrupts from EVENTBATDETECTED)
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTBATLOST			Reserved (Writing 1 disables interrupts from EVENTBATLOST)
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTBATRECHARGE			Writing 1 disables interrupts from EVENTBATRECHARGE
			LOW	0	Low
			HIGH	1	High

EVENTSSHPHLDSET

Address offset: 0x12

SHPHLD pin and watchdog Event Set


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTSHPHLDBTNPRESS			SHPHLD button is pressed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTSHPHLDBTNRELEASE			SHPHLD button is released. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTSHPHLDEXIT			SHPHLD button held to exit Ship mode. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTWATCHDOGWARN			Watchdog timeout warning. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSSHPHLDCLR

Address offset: 0x13

SHPHLD pin and watchdog Event Clear


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTSHPHLDBTNPRESS			SHPHLD button is pressed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTSHPHLDBTNRELEASE			SHPHLD button is released. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTSHPHLDEXIT			SHPHLD button held to exit Ship mode. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTWATCHDOGWARN			Watchdog timeout warning. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSSHPHLDSET

Address offset: 0x14

SHPHLD pin and watchdog Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTSHPHLDBTNPRESS			Writing 1 enables interrupts from EVENTSHPHLDBTNPRESS
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTSHPHLDBTNRELEASE			Writing 1 enables interrupts from EVENTSHPHLDBTNRELEASE
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTSHPHLDEXIT			Writing 1 enables interrupts from EVENTSHPHLDEXIT
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTWATCHDOGWARN			Writing 1 enables interrupts from EVENTWATCHDOGWARN
			LOW	0	Low
			HIGH	1	High

INTENEVENTSSHPHLDCLR

Address offset: 0x15

SHPHLD pin and watchdog Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID										D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTSHPHLDBTNPRESS			Writing 1 disables interrupts from EVENTSHPHLDBTNPRESS
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTSHPHLDBTNRELEASE			Writing 1 disables interrupts from EVENTSHPHLDBTNRELEASE
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTSHPHLDEXIT			Writing 1 disables interrupts from EVENTSHPHLDEXIT
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTWATCHDOGWARN			Writing 1 disables interrupts from EVENTWATCHDOGWARN
			LOW	0	Low
			HIGH	1	High

EVENTSVBUSIN0SET

Address offset: 0x16

VBUS Event Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTVBUSDETECTED			VBUS detected. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTVBUSREMOVED			VBUS removed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTVBUSOVRVOLTDETECTED			VBUS over voltage detected. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTVBUSOVRVOLTREMOVED			VBUS over voltage removed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTVBUSUNDVOLTDETECTED			VBUS under voltage detected. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTVBUSUNDVOLTREMOVED			VBUS under voltage removed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSVBUSIN0CLR

Address offset: 0x17

VBUS Event Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTVBUSDETECTED			VBUS detected. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTVBUSREMOVED			VBUS removed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTVBUSOVRVOLTDETECTED			VBUS over voltage detected. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTVBUSOVRVOLTREMOVED			VBUS over voltage removed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTVBUSUNDVOLTDETECTED			VBUS under voltage detected. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTVBUSUNDVOLTREMOVED			VBUS under voltage removed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSVBUSIN0SET

Address offset: 0x18

VBUS Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTVBUSDETECTED			Writing 1 enables interrupts from EVENTVBUSDETECTED
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTVBUSREMOVED			Writing 1 enables interrupts from EVENTVBUSREMOVED
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTVBUSOVRVOLTDETECTED			Writing 1 enables interrupts from EVENTVBUSOVRVOLTDETECTED
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTVBUSOVRVOLTREMOVED			Writing 1 enables interrupts from EVENTVBUSOVRVOLTREMOVED
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTVBUSUNDVOLTDETECTED			Writing 1 enables interrupts from EVENTVBUSUNDVOLTDETECTED
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTVBUSUNDVOLTREMOVED			Writing 1 enables interrupts from EVENTVBUSUNDVOLTREMOVED
			LOW	0	Low
			HIGH	1	High

INTENEVENTSVBUSIN0CLR

Address offset: 0x19

VBUS Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTVBUSDETECTED			Writing 1 disables interrupts from EVENTVBUSDETECTED
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTVBUSREMOVED			Writing 1 disables interrupts from EVENTVBUSREMOVED
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTVBUSOVRVOLTDETECTED			Writing 1 disables interrupts from EVENTVBUSOVRVOLTDETECTED
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTVBUSOVRVOLTREMOVED			Writing 1 disables interrupts from EVENTVBUSOVRVOLTREMOVED
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTVBUSUNDVOLTDETECTED			Writing 1 disables interrupts from EVENTVBUSUNDVOLTDETECTED
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTVBUSUNDVOLTREMOVED			Writing 1 disables interrupts from EVENTVBUSUNDVOLTREMOVED
			LOW	0	Low
			HIGH	1	High

EVENTSVBUSIN1SET

Address offset: 0x1A

Thermal and charger detection Event Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTTHERMALWARNDETECTED			Thermal warning detected. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTTHERMALWARNREMOVED			Thermal warning removed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTTHERMALSHUTDOWNDETECTED			Thermal shutown detected. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTTHERMALSHUTDOWNREMOVED			Thermal shutdown removed. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTCC1STATECHANGE			Voltage changed on pin CC1. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTCC2STATECHANGE			Voltage changed on pin CC2. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSVBUSIN1CLR

Address offset: 0x1B

Thermal and charger detection Event Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTTHERMALWARNDETECTED			Thermal warning detected. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTTHERMALWARNREMOVED			Thermal warning removed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTTHERMALSHUTDOWNDETECTED			Thermal shutown detected. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTTHERMALSHUTDOWNREMOVED			Thermal shutdown removed. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTCC1STATECHANGE			Voltage changed on pin CC1. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTCC2STATECHANGE			Voltage changed on pin CC2. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSVBUSIN1SET

Address offset: 0x1C

Thermal and charger detection Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTTHERMALWARNDETECTED			Writing 1 enables interrupts from EVENTTHERMALWARNDETECTED
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTTHERMALWARNREMOVED			Writing 1 enables interrupts from EVENTTHERMALWARNREMOVED
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTTHERMALSHUTDOWNDETECTED			Writing 1 enables interrupts from EVENTTHERMALSHUTDOWNDETECTED
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTTHERMALSHUTDOWNREMOVED			Writing 1 enables interrupts from EVENTTHERMALSHUTDOWNREMOVED
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTCC1STATECHANGE			Writing 1 enables interrupts from EVENTCC1STATECHANGE
			LOW	0	Low
			HIGH	1	High
F	RW W1S	EVENTCC2STATECHANGE			Writing 1 enables interrupts from EVENTCC2STATECHANGE
			LOW	0	Low
			HIGH	1	High

INTENEVENTSVBUSIN1CLR

Address offset: 0x1D

Thermal and charger detection Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID								F	E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTTHERMALWARNDETECTED			Writing 1 disables interrupts from EVENTTHERMALWARNDETECTED
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTTHERMALWARNREMOVED			Writing 1 disables interrupts from EVENTTHERMALWARNREMOVED
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTTHERMALSHUTDOWNDETECTED			Writing 1 disables interrupts from EVENTTHERMALSHUTDOWNDETECTED
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTTHERMALSHUTDOWNREMOVED			Writing 1 disables interrupts from EVENTTHERMALSHUTDOWNREMOVED
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTCC1STATECHANGE			Writing 1 disables interrupts from EVENTCC1STATECHANGE
			LOW	0	Low
			HIGH	1	High
F	RW W1C	EVENTCC2STATECHANGE			Writing 1 disables interrupts from EVENTCC2STATECHANGE
			LOW	0	Low
			HIGH	1	High

EVENTSGPIOSET

Address offset: 0x22

GPIO Event Set


Bit number						7	6	5	4	3	2	1	0
ID									E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTGPIOEDGEDETECT0			Edge is detected on GPIO0. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTGPIOEDGEDETECT1			Edge is detected on GPIO1. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTGPIOEDGEDETECT2			Edge is detected on GPIO2. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTGPIOEDGEDETECT3			Edge is detected on GPIO3. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTGPIOEDGEDETECT4			Edge is detected on GPIO4. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 sets the event (for debugging).
			LOW	0	Low
			HIGH	1	High

EVENTSGPIOCLR

Address offset: 0x23

GPIO Event Clear


Bit number						7	6	5	4	3	2	1	0
ID									E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTGPIOEDGEDETECT0			Edge is detected on GPIO0. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTGPIOEDGEDETECT1			Edge is detected on GPIO1. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTGPIOEDGEDETECT2			Edge is detected on GPIO2. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTGPIOEDGEDETECT3			Edge is detected on GPIO3. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTGPIOEDGEDETECT4			Edge is detected on GPIO4. GPIOMODE = 3 : rising edge GPIOMODE = 4 : falling edge. Writing 1 clears the event (e.g. to acknowledge an interrupt).
			LOW	0	Low
			HIGH	1	High

INTENEVENTSGPIOSET

Address offset: 0x24

GPIO Interrupt Enable Set


Bit number						7	6	5	4	3	2	1	0
ID									E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1S	EVENTGPIOEDGEDETECT0			Writing 1 enables interrupts from EVENTGPIOEDGEDETECT0
			LOW	0	Low
			HIGH	1	High
B	RW W1S	EVENTGPIOEDGEDETECT1			Writing 1 enables interrupts from EVENTGPIOEDGEDETECT1
			LOW	0	Low
			HIGH	1	High
C	RW W1S	EVENTGPIOEDGEDETECT2			Writing 1 enables interrupts from EVENTGPIOEDGEDETECT2
			LOW	0	Low
			HIGH	1	High
D	RW W1S	EVENTGPIOEDGEDETECT3			Writing 1 enables interrupts from EVENTGPIOEDGEDETECT3
			LOW	0	Low
			HIGH	1	High
E	RW W1S	EVENTGPIOEDGEDETECT4			Writing 1 enables interrupts from EVENTGPIOEDGEDETECT4
			LOW	0	Low
			HIGH	1	High

INTENEVENTSGPIOCLR

Address offset: 0x25

GPIO Interrupt Enable Clear


Bit number						7	6	5	4	3	2	1	0
ID									E	D	C	B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW W1C	EVENTGPIOEDGEDETECT0			Writing 1 disables interrupts from EVENTGPIOEDGEDETECT0
			LOW	0	Low
			HIGH	1	High
B	RW W1C	EVENTGPIOEDGEDETECT1			Writing 1 disables interrupts from EVENTGPIOEDGEDETECT1
			LOW	0	Low
			HIGH	1	High
C	RW W1C	EVENTGPIOEDGEDETECT2			Writing 1 disables interrupts from EVENTGPIOEDGEDETECT2
			LOW	0	Low
			HIGH	1	High
D	RW W1C	EVENTGPIOEDGEDETECT3			Writing 1 disables interrupts from EVENTGPIOEDGEDETECT3
			LOW	0	Low
			HIGH	1	High
E	RW W1C	EVENTGPIOEDGEDETECT4			Writing 1 disables interrupts from EVENTGPIOEDGEDETECT4
			LOW	0	Low
			HIGH	1	High

REVISIONMSB

Address offset: 0x26

Revision MSB. See nPM1304 Compatibility Matrix for details.


Bit number						7	6	5	4	3	2	1	0
ID						A	A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	R	REVMSB			Revision MSB

REVISIONLSB

Address offset: 0x27

Revision LSB. See nPM1304 Compatibility Matrix for details.


Bit number						7	6	5	4	3	2	1	0
ID						A	A	A	A	A	A	A	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	R	REVLSB			Revision LSB