RESET — Reset control

The SHPHLD pin is a reset control, in addition to being used for exiting Ship and Hibernate mode.

The SHPHLD pin has an internal pull-up resistor R_SHPHLD to VBAT or VBUS depending on which has the highest voltage. The functionality of the pin is determined by the device mode.

Normal operation

If configured, a short logic-low pulse on SHPHLD sends an interrupt to the host. Host software reads the pin state in register SHPHLDSTATUS.

A long logic-low (> t_RESETBUT ) on SHPHLD causes a power cycle and resets the whole system. This feature is enabled by default after power-up, but can be disabled by the host software. See register LPRESETCONFIG for more information.

Ship and Hibernate modes

When a logic-low occurs for longer than t_shipToActive, the device wakes up from Ship or Hibernate mode, performs an internal reset, and transitions to normal operation.

Two-button reset

A two-button reset is implemented by connecting one button to the SHPHLD pin and another button to GPIO0. This feature is enabled by setting LPRESETCONFIG, and then TASKSHPHLDCFGSTROBE to apply the configured value. In addition, GPIO0 needs to be configured as input using GPIOMODE[0] and the internal pull-down needs to be disabled in GPIOPDEN[0]. Internal pull-up can be enabled in GPIOPUEN[0] in case there is no external pull-up resistor. Pressing and holding both buttons for longer than t_RESETBUT starts a power cycle.

Host software reset

Host software can reset the device by writing the TASKSWRESET bit in register TASKSWRESET. As a consequence, a power cycle is performed. A reset is not possible in Ship or Hibernate mode.

Scratch registers, reason for reset

Only POR and TASKCLRERRLOG can initialize the context registers found at SCRATCH[n]. The cause of the first reset is reported in register RSTCAUSE.