Ship and Hibernate modes

Ship and Hibernate modes isolate the battery from the system and minimize the quiescent current.

Hibernate mode is identical to Ship mode with the exception that, in Hibernate mode, the timer is running and functions as an additional wake-up source.

The device enters Ship mode through register TASKENTERSHIPMODE. Register SHPHLDCONFIG configures the SHPHLD button press time, and register TASKSHPHLDCFGSTROBE applies the configured value. When VBUS is not present, the device enters Ship mode immediately. The host software must wait until EVENTSVBUSIN0SET to ensure VBUS is disconnected and discharged before writing to the register.

The device enters Hibernate mode through register TASKENTERHIBERNATE. The host software must wait until EVENTSVBUSIN0SET to ensure VBUS is disconnected and discharged before writing to the register. To apply the timer value, registers TIMERHIBYTE, TIMERMIDBYTE, and TIMERLOBYTE must be configured before register TIMERTARGETSTROBE. In Hibernate mode, the quiescent current is higher compared to Ship mode because the low-power timer is running.

Exiting Hibernate mode using a button press must be configured in register SHPHLDCONFIG and TASKSHPHLDCFGSTROBE.

When entering Ship mode, BUCK can be configured to discharge by enabling their pull downs, see BUCKCTRL0.

Note: SHPHLDCONFIG and TASKSHPHLDCFGSTROBE must be set before entering either Ship or Hibernate modes.

The following are alternative ways to exit Ship and Hibernate modes.

Pulling pin SHPHLD low for a minimum period of t_shipToActive (see SHPHLDCONFIG). A push button to GND is required.
Applying a voltage on VBUS > VBUS_POR.
Exiting automatically through the Wake-up timer (only from Hibernate mode).

Electrical specification

Table 1. Ship mode electrical specification
Symbol	Description	Min.	Typ.	Max.	Unit
t_shipToActive	Duration SHPHLD pin must be held low to exit Ship or Hibernate mode		16 32 64 96 (default) 304 608 1008 3008		ms
V_IL	Input low voltage for SHPHLD pin	AVSS		0.4	V
V_IH	Input high voltage for SHPHLD pin	1.2		VBAT	V
t_RESETBUT	Amount of time for a button press to cause a power cycle		10		s
R_SHPHLD	Pull-up resistor on SHPHLD pin		50		kΩ

Registers

Instances


Instance	Base address	Description
SHIP	0x00000B00	SHIP registers SHPHLD register map

Register overview


Register	Offset	Description
TASKENTERHIBERNATE	0x0	Enter Hibernate
TASKSHPHLDCFGSTROBE	0x1	Load SHPHLD configuration
TASKENTERSHIPMODE	0x2	Enter Ship mode
TASKRESETCFG	0x3	Reset configuration
SHPHLDCONFIG	0x4	Configuration for SHPHLD
SHPHLDSTATUS	0x5	Status of the SHPHLD pin
LPRESETCONFIG	0x6	Long press reset configuration

TASKENTERHIBERNATE

Address offset: 0x0

Enter Hibernate


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKENTERHIBERNATE			Enter Hibernate (Ship mode with Wake-up timer)
			NOEFFECT	0	No effect
			TRIGGER	1	Trigger task

TASKSHPHLDCFGSTROBE

Address offset: 0x1

Load SHPHLD configuration


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKSHPHLDCONFIGSTROBE			Load the SHPHLD configuration
			NOEFFECT	0	No effect
			TRIGGER	1	Strobe config

TASKENTERSHIPMODE

Address offset: 0x2

Enter Ship mode


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKENTERSHIPMODE			Enter Ship mode (without Wake-up timer)
			NOEFFECT	0	No effect
			TRIGGER	1	Trigger task

TASKRESETCFG

Address offset: 0x3

Reset configuration


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	W	TASKSHPHLDRSTCONFIG			Reset configuration settings
			NOEFFECT	0	No effect
			TRIGGER	1	Reset

SHPHLDCONFIG

Address offset: 0x4

Configuration for SHPHLD


Bit number						7	6	5	4	3	2	1	0
ID											A	A	A
Reset 0x03						0	0	0	0	0	0	1	1
ID	R/W	Field	Value ID	Value	Description
A	RW	SHPHLDTIM			Configuration for SHPHLD debounce
			16ms	0	16 ms
			32ms	1	32 ms
			64ms	2	64 ms
			96ms	3	96 ms (default)
			304ms	4	304 ms
			608ms	5	608 ms
			1008ms	6	1008 ms
			3008ms	7	3008 ms

SHPHLDSTATUS

Address offset: 0x5

Status of the SHPHLD pin


Bit number						7	6	5	4	3	2	1	0
ID													A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	R	SHPHLDPINSTATUS			SHPHLD pin status
			LOW	0	Low
			HIGH	1	High

LPRESETCONFIG

Address offset: 0x6

Long press reset configuration


Bit number						7	6	5	4	3	2	1	0
ID												B	A
Reset 0x00						0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value	Description
A	RW	LONGTIMRESETDIS			Long press reset disable
			ENABLED	0	Long press reset enabled
			DISABLED	1	Long press reset disabled
B	RW	LONGTIMTWOBUTTONSEL			Select one (default) or two buttons to perform long press reset
			SHPHLD	0	One button (SHPHLD)
			SHPHLDGPIO0	1	Two buttons (SHPHLD and GPIO0)