To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from the product page for the nRF52833 on www.nordicsemi.com.

In this section there are reference circuits for QIAA aQFN73™, CJAA WLCSP, and QDAA QFN40 packages, showing the components and component values to support on-chip features in a design.

Note: This is not a complete list of configurations, but all required circuitry is shown for further configurations.
Some general guidance is summarized here:
  • When supplying power from a USB source only, VBUS must be connected to VDDH if USB is to be used.
  • Components required for DC/DC function are only needed if DC/DC mode is enabled for that regulator.
  • NFC can be used in any configuration.
  • USB can be used in any configuration as long as VBUS is supplied by the USB host.
  • The schematics include an optional series resistor on the USB supply for improved immunity to transient overvoltage during VBUS connection. Using the series resistor is recommended for new designs.

Circuit configurations for QIAA aQFN73

Table 1. Circuit configurations
Config no. Supply configuration Features that can be enabled for each configuration example
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Config. 2 Battery/Ext. regulator N/A No Yes No
Config. 3 N/A Battery/Ext. regulator No Yes No
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Config. 6 N/A Battery/Ext. regulator No No No

Circuit configurations for QDAA QFN40

Table 2. Circuit configurations
Config no. Supply configuration Features that can be enabled for each configuration example
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Config. 2 Battery/Ext. regulator N/A No Yes No
Config. 3 N/A Battery/Ext. regulator No Yes No
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Config. 6 N/A Battery/Ext. regulator No No No

Circuit configurations for CJAA WLCSP

Table 3. Circuit configurations
Config no. Supply configuration Features that can be enabled for each configuration example
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Config. 2 Battery/Ext. regulator N/A No Yes No
Config. 3 N/A Battery/Ext. regulator No Yes No
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Config. 6 N/A Battery/Ext. regulator No No No

Circuit configuration no. 1 for QIAA aQFN73

Circuit configuration number 1 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 4. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Figure 1. Circuit configuration no. 1 schematic

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QIAA Ref. Layout (LDO only, VBUS supply) 1.1 26.05.2021 nrf52833_qiaa_var1.SchDoc 1 1 RUBR A4 X1 32MHz C1 12pF C2 12pF C11 100pF C5 100nF C19 4.7 µ F XC1 XC2 VDD_nRF P0.07 P0.10/NFC2 P0.11 P0.12 P 0 . 1 8 / R E S E T DEC1 SWDCLK SWDIO C14 1.0 µ F P1.09 C10 N.C. P0.00/XL1 P0.01/XL2 P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P0.09/NFC1 C17 12pF C16 12pF X2 32.768kHz Optional VDD_nRF C7 100nF D + D - VDD_nRF C8 100nF Not required for Bxx and later C9 820pF P0.08 P1.08 P0.06 P0.26 P0.27 P 0 . 1 3 P 0 . 1 4 P 0 . 1 5 P 0 . 1 6 P 0 . 1 7 C12 100nF VDD_nRF P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C18 4.7 µ F C13 1.0 µ F C6 4.7 µ F DEC4_6 D E C 4 _ 6 P 1 . 0 0 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P 0 . 2 2 P 0 . 2 3 RF P1.01 P1.02 P 1 . 0 3 P1.04 P 1 . 0 5 P1.06 P1.07 P 0 . 2 5 P 0 . 2 4 C3 1.0pF L1 4.7nH C4 1.2pF DEC1 C1 VDD W1 VSS_PA F23 ANT H23 DEC6 E24 DEC3 D23 XC1 B24 XC2 A23 V D D A 2 2 P 0 . 2 5 A 2 0 P0.00/XL1 D2 P0.01/XL2 F2 P 0 . 2 8 / A I N 4 B 1 1 D E C 4 B 5 V S S B 7 V D D B 1 D C C B 3 SWDCLK AA24 SWDIO AC24 P1.01 Y23 D - A D 4 nRF52833 VDDH Y2 V B U S A D 2 DECUSB AC5 D + A D 6 P 0 . 2 0 A D 1 6 P 0 . 2 1 A C 1 7 P 0 . 2 2 A D 1 8 P 0 . 2 4 A D 2 0 VDD AD23 P0.09/NFC1 L24 P1.09 R1 P 1 . 0 0 A D 2 2 P0.26 G1 P0.27 H2 P0.04/AIN2 J1 P0.05/AIN3 K2 P0.06 L1 P0.07 M2 P0.08 N1 P1.08 P2 P 0 . 1 3 A D 8 P 0 . 1 4 A C 9 P 0 . 1 5 A D 1 0 P 0 . 1 6 A C 1 1 P0.11 T2 P0.12 U1 P 0 . 1 7 A D 1 2 P 0 . 1 8 / R E S E T A C 1 3 DEC5 N24 P0.10/NFC2 J24 P 0 . 0 3 / A I N 1 B 1 3 P 0 . 0 2 / A I N 0 A 1 2 P 0 . 2 9 / A I N 5 A 1 0 P 0 . 3 0 / A I N 6 B 9 P 0 . 3 1 / A I N 7 A 8 V D D A D 1 4 P1.02 W24 P1.04 U24 P1.06 R24 P1.07 P23 P 0 . 2 3 B 1 7 P 1 . 0 5 A 1 6 P 1 . 0 3 B 1 5 P 0 . 1 9 A 1 4 V S S 7 4 N.C. AB2 N . C . A C 1 5 N . C . A C 1 9 N . C . A C 2 1 N.C. V23 N.C. T23 N . C . B 1 9 N . C . A 1 8 U1 nRF52833-QIAA L2 2.2nH VBUS_nRF VBUS Optional VBUS_nRF R1 2R2

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 5. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
C18 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
R1 2R2 Resistor, ±1%, 0.063 W 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth® low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 2 for QIAA aQFN73

Circuit configuration number 2 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 6. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 2 Battery/Ext. regulator N/A No Yes No
Figure 2. Circuit configuration no. 2 schematic

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QIAA Ref. Layout (LDO only, VDDH supply) 1.1 26.05.2021 nrf52833_qiaa_var2.SchDoc 1 1 RUBR A4 C20 4.7 µ F X1 32MHz C1 12pF C2 12pF C11 100pF C5 100nF C19 4.7 µ F XC1 XC2 VDD_nRF P0.07 P0.10/NFC2 P0.11 P0.12 P 0 . 1 8 / R E S E T DEC1 SWDCLK SWDIO C14 1.0 µ F P1.09 C10 N.C. P0.00/XL1 P0.01/XL2 P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 VBUS VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P0.09/NFC1 C17 12pF C16 12pF X2 32.768kHz Optional VDD_nRF C7 100nF D + D - VDD_nRF C8 100nF Not required for Bxx and later C9 820pF P0.08 P1.08 P0.06 P0.26 P0.27 P 0 . 1 3 P 0 . 1 4 P 0 . 1 5 P 0 . 1 6 P 0 . 1 7 C12 100nF VDD_nRF P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C18 4.7 µ F C13 1.0 µ F C6 4.7 µ F VDDH DEC4_6 D E C 4 _ 6 P 1 . 0 0 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P 0 . 2 2 P 0 . 2 3 RF P1.01 P1.02 P 1 . 0 3 P1.04 P 1 . 0 5 P1.06 P1.07 P 0 . 2 5 P 0 . 2 4 L1 4.7nH DEC1 C1 VDD W1 VSS_PA F23 ANT H23 DEC6 E24 DEC3 D23 XC1 B24 XC2 A23 V D D A 2 2 P 0 . 2 5 A 2 0 P0.00/XL1 D2 P0.01/XL2 F2 P 0 . 2 8 / A I N 4 B 1 1 D E C 4 B 5 V S S B 7 V D D B 1 D C C B 3 SWDCLK AA24 SWDIO AC24 P1.01 Y23 D - A D 4 nRF52833 VDDH Y2 V B U S A D 2 DECUSB AC5 D + A D 6 P 0 . 2 0 A D 1 6 P 0 . 2 1 A C 1 7 P 0 . 2 2 A D 1 8 P 0 . 2 4 A D 2 0 VDD AD23 P0.09/NFC1 L24 P1.09 R1 P 1 . 0 0 A D 2 2 P0.26 G1 P0.27 H2 P0.04/AIN2 J1 P0.05/AIN3 K2 P0.06 L1 P0.07 M2 P0.08 N1 P1.08 P2 P 0 . 1 3 A D 8 P 0 . 1 4 A C 9 P 0 . 1 5 A D 1 0 P 0 . 1 6 A C 1 1 P0.11 T2 P0.12 U1 P 0 . 1 7 A D 1 2 P 0 . 1 8 / R E S E T A C 1 3 DEC5 N24 P0.10/NFC2 J24 P 0 . 0 3 / A I N 1 B 1 3 P 0 . 0 2 / A I N 0 A 1 2 P 0 . 2 9 / A I N 5 A 1 0 P 0 . 3 0 / A I N 6 B 9 P 0 . 3 1 / A I N 7 A 8 V D D A D 1 4 P1.02 W24 P1.04 U24 P1.06 R24 P1.07 P23 P 0 . 2 3 B 1 7 P 1 . 0 5 A 1 6 P 1 . 0 3 B 1 5 P 0 . 1 9 A 1 4 V S S 7 4 N.C. AB2 N . C . A C 1 5 N . C . A C 1 9 N . C . A C 2 1 N.C. V23 N.C. T23 N . C . B 1 9 N . C . A 1 8 U1 nRF52833-QIAA L2 2.2nH C3 1.0pF C4 1.2pF

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 7. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
C18, C19 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 3 for QIAA aQFN73

Circuit configuration number 3 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 8. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 3 N/A Battery/Ext. regulator No Yes No
Figure 3. Circuit configuration no. 3 schematic

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QIAA Ref. Layout (LDO only, VDD supply) 1.1 26.05.2021 nrf52833_qiaa_var3.SchDoc 1 1 RUBR A4 C20 4.7 µ F X1 32MHz C1 12pF C2 12pF C11 100pF C5 100nF C19 4.7 µ F XC1 XC2 VDD_nRF P0.07 P0.10/NFC2 P0.11 P0.12 P 0 . 1 8 / R E S E T DEC1 SWDCLK SWDIO C14 1.0 µ F P1.09 C10 N.C. P0.00/XL1 P0.01/XL2 P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 VBUS VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P0.09/NFC1 C17 12pF C16 12pF X2 32.768kHz Optional VDD_nRF C7 100nF D + D - VDD_nRF C8 100nF Not required for Bxx and later C9 820pF P0.08 P1.08 P0.06 P0.26 P0.27 P 0 . 1 3 P 0 . 1 4 P 0 . 1 5 P 0 . 1 6 P 0 . 1 7 C12 100nF VDD_nRF P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C13 1.0 µ F C6 4.7 µ F DEC4_6 D E C 4 _ 6 P 1 . 0 0 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P 0 . 2 2 P 0 . 2 3 RF P1.01 P1.02 P 1 . 0 3 P1.04 P 1 . 0 5 P1.06 P1.07 P 0 . 2 5 P 0 . 2 4 L1 4.7nH DEC1 C1 VDD W1 VSS_PA F23 ANT H23 DEC6 E24 DEC3 D23 XC1 B24 XC2 A23 V D D A 2 2 P 0 . 2 5 A 2 0 P0.00/XL1 D2 P0.01/XL2 F2 P 0 . 2 8 / A I N 4 B 1 1 D E C 4 B 5 V S S B 7 V D D B 1 D C C B 3 SWDCLK AA24 SWDIO AC24 P1.01 Y23 D - A D 4 nRF52833 VDDH Y2 V B U S A D 2 DECUSB AC5 D + A D 6 P 0 . 2 0 A D 1 6 P 0 . 2 1 A C 1 7 P 0 . 2 2 A D 1 8 P 0 . 2 4 A D 2 0 VDD AD23 P0.09/NFC1 L24 P1.09 R1 P 1 . 0 0 A D 2 2 P0.26 G1 P0.27 H2 P0.04/AIN2 J1 P0.05/AIN3 K2 P0.06 L1 P0.07 M2 P0.08 N1 P1.08 P2 P 0 . 1 3 A D 8 P 0 . 1 4 A C 9 P 0 . 1 5 A D 1 0 P 0 . 1 6 A C 1 1 P0.11 T2 P0.12 U1 P 0 . 1 7 A D 1 2 P 0 . 1 8 / R E S E T A C 1 3 DEC5 N24 P0.10/NFC2 J24 P 0 . 0 3 / A I N 1 B 1 3 P 0 . 0 2 / A I N 0 A 1 2 P 0 . 2 9 / A I N 5 A 1 0 P 0 . 3 0 / A I N 6 B 9 P 0 . 3 1 / A I N 7 A 8 V D D A D 1 4 P1.02 W24 P1.04 U24 P1.06 R24 P1.07 P23 P 0 . 2 3 B 1 7 P 1 . 0 5 A 1 6 P 1 . 0 3 B 1 5 P 0 . 1 9 A 1 4 V S S 7 4 N.C. AB2 N . C . A C 1 5 N . C . A C 1 9 N . C . A C 2 1 N.C. V23 N.C. T23 N . C . B 1 9 N . C . A 1 8 U1 nRF52833-QIAA L2 2.2nH C3 1.0pF C4 1.2pF

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 9. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
C20 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 4 for QIAA aQFN73

Circuit configuration number 4 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 10. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Figure 4. Circuit configuration no. 4 schematic for QIAA aQFN73
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 11. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
C15 47 nF Capacitor, X7R, ±10% 0402
C18, C20 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
L3 10 µH Chip inductor, IDC min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor ±10% 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 5 for QIAA aQFN73

Circuit configuration number 5 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 12. Configuration summary for circuit configuration no. 5
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Figure 5. Circuit configuration no. 5 schematic
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 13. Bill of material for circuit configuration no. 5
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
C15 47 nF Capacitor, X7S, ±10% 0402
C20 4.7 µF Capacitor, X7S, ±10% 0603
Ctune1, Ctune2 Antenna dependent Capacitor, NP0, ±5% 0402
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
L3 10 µH Chip inductor, IDC min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor ±10% 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 6 for QIAA aQFN73

Circuit configuration number 6 for QIAA aQFN73, showing the schematic and the bill of materials table.

Table 14. Configuration summary for circuit configuration no. 6
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 6 N/A Battery/Ext. regulator No No No
Figure 6. Circuit configuration no. 6 schematic

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QIAA Ref. Layout (LDO only, VDD supply, No USB) 1.1 26.05.2021 nrf52833_qiaa_var6.SchDoc 1 1 RUBR A4 X1 32MHz C1 12pF C2 12pF C11 100pF C5 100nF XC1 XC2 VDD_nRF P0.07 P0.10/NFC2 P0.11 P0.12 P 0 . 1 8 / R E S E T DEC1 SWDCLK SWDIO C14 1.0 µ F P1.09 C10 N.C. P0.00/XL1 P0.01/XL2 P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P0.09/NFC1 C17 12pF C16 12pF X2 32.768kHz Optional VDD_nRF C7 100nF VDD_nRF C8 100nF Not required for Bxx and later C9 820pF P0.08 P1.08 P0.06 P0.26 P0.27 P 0 . 1 3 P 0 . 1 4 P 0 . 1 5 P 0 . 1 6 P 0 . 1 7 C12 100nF VDD_nRF P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C13 1.0 µ F C6 4.7 µ F DEC4_6 D E C 4 _ 6 P 1 . 0 0 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P 0 . 2 2 P 0 . 2 3 RF P1.01 P1.02 P 1 . 0 3 P1.04 P 1 . 0 5 P1.06 P1.07 P 0 . 2 5 P 0 . 2 4 L1 4.7nH DEC1 C1 VDD W1 VSS_PA F23 ANT H23 DEC6 E24 DEC3 D23 XC1 B24 XC2 A23 V D D A 2 2 P 0 . 2 5 A 2 0 P0.00/XL1 D2 P0.01/XL2 F2 P 0 . 2 8 / A I N 4 B 1 1 D E C 4 B 5 V S S B 7 V D D B 1 D C C B 3 SWDCLK AA24 SWDIO AC24 P1.01 Y23 D - A D 4 nRF52833 VDDH Y2 V B U S A D 2 DECUSB AC5 D + A D 6 P 0 . 2 0 A D 1 6 P 0 . 2 1 A C 1 7 P 0 . 2 2 A D 1 8 P 0 . 2 4 A D 2 0 VDD AD23 P0.09/NFC1 L24 P1.09 R1 P 1 . 0 0 A D 2 2 P0.26 G1 P0.27 H2 P0.04/AIN2 J1 P0.05/AIN3 K2 P0.06 L1 P0.07 M2 P0.08 N1 P1.08 P2 P 0 . 1 3 A D 8 P 0 . 1 4 A C 9 P 0 . 1 5 A D 1 0 P 0 . 1 6 A C 1 1 P0.11 T2 P0.12 U1 P 0 . 1 7 A D 1 2 P 0 . 1 8 / R E S E T A C 1 3 DEC5 N24 P0.10/NFC2 J24 P 0 . 0 3 / A I N 1 B 1 3 P 0 . 0 2 / A I N 0 A 1 2 P 0 . 2 9 / A I N 5 A 1 0 P 0 . 3 0 / A I N 6 B 9 P 0 . 3 1 / A I N 7 A 8 V D D A D 1 4 P1.02 W24 P1.04 U24 P1.06 R24 P1.07 P23 P 0 . 2 3 B 1 7 P 1 . 0 5 A 1 6 P 1 . 0 3 B 1 5 P 0 . 1 9 A 1 4 V S S 7 4 N.C. AB2 N . C . A C 1 5 N . C . A C 1 9 N . C . A C 2 1 N.C. V23 N.C. T23 N . C . B 1 9 N . C . A 1 8 U1 nRF52833-QIAA L2 2.2nH C3 1.0pF C4 1.2pF

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 15. Bill of material for circuit configuration no. 6
Designator Value Description Footprint
C1, C2, C16, C17 12 pF Capacitor, NP0, ±2% 0402
C3 1.0 pF Capacitor, NP0, ±5% 0402
C4 1.2 pF Capacitor, NP0, ±5% 0402
C5, C7, C8, C12 100 nF Capacitor, X7R, ±10% 0402
C6 4.7 µF Capacitor, X7R, ±10% 0603
C9 820 pF

Capacitor, NP0, ±5%

Not required for Bxx and later

 0402
C10 N.C. Not mounted 0402
C11 100 pF Capacitor, NP0, ±5% 0402
C13, C14 1.0 µF Capacitor, X7R, ±10% 0603
L1 4.7 nH High frequency chip inductor ±5% 0402
L2 2.2 nH High frequency chip inductor ±5% 0402
U1 nRF52833-QIAA Multiprotocol Bluetooth low energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip AQFN-73
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_3215

Circuit configuration no. 1 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 1.

Table 16. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Figure 7. Circuit configuration no. 1 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (LDO only, VBUS supply) 1.1 26.05.2021 nrf52833_qdaa_var1.SchDoc 1 1 RUBR A4 P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F C9 N.C. DEC3 VDD_nRF C7 100nF C11 100nF VDD_nRF C12 1.0 µ F DEC4_6 D E C 4 _ 6 RF C19 4.7 µ F VDD_nRF D + D - C6 4.7 µ F P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH Not required for Bxx and later C8 820pF P0.09/NFC1 P0.10/NFC2 P 0 . 1 8 / R E S E T S W D C L K S W D I O P 0 . 1 5 P 0 . 1 7 P 0 . 2 0 C5 100nF DEC1 VBUS C17 4.7 µ F Optional R1 2R2

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 17. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
C17 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
R1 2R2 Resistor, ±1%, 0.063 W 0402
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 2 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 2.

Table 18. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 2 Battery/Ext. regulator N/A No Yes No
Figure 8. Circuit configuration no. 2 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (LDO only, VDDH supply) 1.1 26.05.2021 nrf52833_qdaa_var2.SchDoc 1 1 RUBR A4 P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F C9 N.C. VBUS DEC3 VDD_nRF C7 100nF C18 4.7 µ F C11 100nF VDD_nRF C12 1.0 µ F DEC4_6 D E C 4 _ 6 RF C19 4.7 µ F VDD_nRF D + D - C17 4.7 µ F C6 4.7 µ F VDDH P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH Not required for Bxx and later C8 820pF P0.09/NFC1 P0.10/NFC2 P 0 . 1 8 / R E S E T S W D C L K S W D I O P 0 . 1 5 P 0 . 1 7 P 0 . 2 0 C5 100nF DEC1

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 19. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
C17, C18 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 3 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 3.

Table 20. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 3 N/A Battery/Ext. regulator No Yes No
Figure 9. Circuit configuration no. 3 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (LDO only, VDD supply) 1.1 26.05.2021 nrf52833_qdaa_var3.SchDoc 1 1 RUBR A4 P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F C9 N.C. VBUS DEC3 VDD_nRF C7 100nF C18 4.7 µ F C11 100nF VDD_nRF C12 1.0 µ F DEC4_6 D E C 4 _ 6 RF C19 4.7 µ F VDD_nRF D + D - C6 4.7 µ F P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH Not required for Bxx and later C8 820pF P0.09/NFC1 P0.10/NFC2 P 0 . 1 8 / R E S E T S W D C L K S W D I O P 0 . 1 5 P 0 . 1 7 P 0 . 2 0 C5 100nF DEC1

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 21. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
C18 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 4 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 4.

Table 22. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Figure 10. Circuit configuration no. 4 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (DCDC, VDDH supply) 1.1 26.05.2021 nrf52833_qdaa_var4.SchDoc 1 1 RUBR A4 P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F L4 15nH C9 N.C. VBUS DEC3 VDD_nRF C7 100nF C18 4.7 µ F Not required for Bxx and later C8 820pF C11 100nF VDD_nRF C12 1.0 µ F P0.09/NFC1 P0.10/NFC2 C14 47nF DEC4_6 D E C 4 _ 6 RF C19 4.7 µ F VDD_nRF D + D - C17 4.7 µ F C6 4.7 µ F VDDH P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 L3 10 µ H C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH P 0 . 1 8 / R E S E T S W D C L K S W D I O P 0 . 1 5 P 0 . 1 7 P 0 . 2 0 C5 100nF DEC1

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 23. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
C14 47 nF Capacitor, X7S, ±10% 0201
C17, C18 4.7 µF Capacitor, X7S, ±10% 0603
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor, ±10% 0402
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 5 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 5.

Table 24. Configuration summary for circuit configuration no. 5
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Figure 11. Circuit configuration no. 5 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (DCDC, VDD supply, NFC) 1.1 26.05.2021 nrf52833_qdaa_var5.SchDoc 1 1 RUBR A4 P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F L4 15nH C9 N.C. VBUS DEC3 VDD_nRF C7 100nF C18 4.7 µ F Not required for Bxx and later C8 820pF C11 100nF VDD_nRF C12 1.0 µ F NFC1 NFC2 Ctune1 TBD Ctune2 TBD Note: The value of Ctune1 and Ctune2 must be tuned to match the selected NFC antenna. C14 47nF DEC4_6 D E C 4 _ 6 RF C19 4.7 µ F VDD_nRF D + D - C6 4.7 µ F P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 L3 10 µ H C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH P 0 . 1 8 / R E S E T S W D C L K S W D I O P 0 . 1 5 P 0 . 1 7 P 0 . 2 0 C5 100nF DEC1

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 25. Bill of material for circuit configuration no. 5
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6, C19 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
C14 47 nF Capacitor, X7S, ±10% 0201
C18 4.7 µF Capacitor, X7S, ±10% 0603
Ctune1, Ctune2 TBD Capacitor, X7R, ±10% 0201
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor, ±10% 0402
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 6 for QDAA QFN40

This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 6.

Table 26. Configuration summary for circuit configuration no. 6
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 6 N/A Battery/Ext. regulator No No No
Figure 12. Circuit configuration no. 6 schematic for QDAA QFN40

image/svg+xml 1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52833-QDAA Ref. Layout (LDO only, VDD supply, No USB) 1.1 26.05.2021 nrf52833_qdaa_var6.SchDoc 1 1 RUBR A4 C5 100nF P 0 . 1 8 / R E S E T DEC1 S W D C L K S W D I O P1.09 P0.00/XL1 P0.01/XL2 DEC1 1 VSS 25 ANT 24 DEC6 26 DEC3 27 XC1 28 XC2 29 VDD 30 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.11 7 P 0 . 2 8 / A I N 4 3 3 P 0 . 2 9 / A I N 5 3 4 P 0 . 3 0 / A I N 6 3 5 P 0 . 3 1 / A I N 7 3 6 D E C 4 3 8 V S S 3 7 V D D 4 0 D C C 3 9 S W D C L K 2 0 S W D I O 1 9 P 0 . 1 5 1 4 P 0 . 1 7 1 5 nRF52833 VDD 8 D - 1 2 VDDH 9 VBUS 10 D E C U S B 1 1 D + 1 3 V D D 1 8 P0.09/NFC1 22 P1.09 6 P 0 . 1 8 / R E S E T 1 6 DEC5 21 P0.10/NFC2 23 P 0 . 0 3 / A I N 1 3 1 P 0 . 0 2 / A I N 0 3 2 P 0 . 2 0 1 7 V S S 4 1 U1 nRF52833-QDAA P0.04/AIN2 P0.05/AIN3 P 0 . 1 5 P 0 . 1 7 P0.11 C16 12pF C15 12pF X2 32.768kHz Optional X1 32MHz C1 12pF C2 12pF C10 100pF XC1 XC2 VDD_nRF C13 1.0 µ F C9 N.C. DEC3 VDD_nRF C7 100nF C11 100nF VDD_nRF C12 1.0 µ F DEC4_6 D E C 4 _ 6 RF VDD_nRF C6 4.7 µ F P 0 . 0 2 / A I N 0 P 0 . 0 3 / A I N 1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 P 0 . 2 0 C3 1.0pF L1 4.7nH C4 1.2pF L2 2.2nH Not required for Bxx and later C8 820pF P0.09/NFC1 P0.10/NFC2

Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 27. Bill of material for circuit configuration no. 6
Designator Value Description Footprint
C1, C2, C15, C16 12 pF Capacitor, NP0, ±2% 0201
C3 1.0 pF Capacitor, NP0, ±5% 0201
C4 1.2 pF Capacitor, NP0, ±5% 0201
C5, C7, C11 100 nF Capacitor, X7S, ±10% 0201
C6 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C9 N.C. Not mounted 0201
C10 100 pF Capacitor, NP0, ±5% 0201
C12, C13 1.0 µF Capacitor, X7S, ±10% 0402
L1 4.7 nH High frequency chip inductor, ±5% 0201
L2 2.2 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-QDAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip QFN-40
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 1 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 1.

Table 28. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 1 USB (VDDH = VBUS) N/A No Yes No
Figure 13. Circuit configuration no. 1 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 29. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5, C16 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
C15 4.7 µF Capacitor, X7S, ±10% 0603
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
R1 2R2 Resistor, ±1%, 0.05W 0201
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 2 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 2.

Table 30. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 2 Battery/Ext. regulator N/A No Yes No
Figure 14. Circuit configuration no. 2 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 31. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5, C16 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
C15, C17 4.7 µF Capacitor, X7S, ±10% 0603
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 3 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 3.

Table 32. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 3 N/A Battery/Ext. regulator No Yes No
Figure 15. Circuit configuration no. 3 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 33. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5, C16 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
C17 4.7 µF Capacitor, X7S, ±10% 0603
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 4 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 4.

Table 34. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 4 Battery/Ext. regulator N/A Yes Yes No
Figure 16. Circuit configuration no. 4 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 35. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5, C16 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
C12 47 nF Capacitor, X7S, ±10% 0201
C15, C17 4.7 µF Capacitor, X7S, ±10% 0603
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor, ±10% 0402
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 5 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 5.

Table 36. Configuration summary for circuit configuration no. 5
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 5 N/A Battery/Ext. regulator Yes Yes Yes
Figure 17. Circuit configuration no. 5 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 37. Bill of material for circuit configuration no. 5
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5, C16 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
C12 47 nF Capacitor, X7S, ±10% 0201
C17 4.7 µF Capacitor, X7S, ±10% 0603
CT1, CT2, CT3, CT4 Antenna dependent Capacitor, X7R, ± 10 % 0201
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L4 15 nH High frequency chip inductor, ±10% 0402
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 6 for CJAA WLCSP

This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 6.

Table 38. Configuration summary for circuit configuration no. 6
Config no. Supply configuration Enabled features
VDDH VDD DCDCEN1 USB NFC
Config. 6 N/A Battery/Ext. regulator No No No
Figure 18. Circuit configuration no. 6 schematic for CJAA WLCSP
Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.
Table 39. Bill of material for circuit configuration no. 6
Designator Value Description Footprint
C1, C2, C13, C14 12 pF Capacitor, NP0, ±2% 0201
C3 0.8 pF Capacitor, NP0, ±5% 0201
C4, C6, C7, C9 100 nF Capacitor, X7S, ±10% 0201
C5 4.7 µF Capacitor, X7R, ±10% 0603
C8 820 pF

Capacitor, X7R, ±10%

Not required for Bxx and later

 0201
C10, C11 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor, ±5% 0201
L2 5.6 nH High frequency chip inductor, ±5% 0201
U1 nRF52833-CJAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4 GHz proprietary System on Chip WLCSP-75
X1 32 MHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: ±40 ppm XTAL_1612
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

PCB guidelines

A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.com.

To ensure optimal performance it is essential that you follow the schematics and layout references closely. Especially in the case of the antenna matching circuitry (components between device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All reference circuits are designed for use with a 50 Ω single-ended antenna.

A PCB with a minimum of four layers, including a ground plane, is recommended for optimal performance. Put a keep-out area on the inner layers directly below the antenna matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 Ω) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended package reference circuitry in Reference circuitry.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive loading of fast switching digital output lines should be minimized in order to avoid radio interference.

PCB layout example

The PCB layout shown in the following figures is a reference layout for the aQFN™ package with internal LDO setup and VBUS supply.

Note: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the ground plane, but grounded via VSS_PA pin F23. This is done to create additional filtering of harmonic components.

For all available reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.

Figure 19. Top silk layer


Figure 20. Top layer


Figure 21. Mid layer 1


Figure 22. Mid layer 2


Figure 23. Bottom layer


Note: No components in bottom layer.

PMIC support

The nRF52 Series is comprehensively supported by Nordic Semiconductor's own range of PMICs (Power Management Integrated Circuits). These PMICs are meticulously designed to enhance the performance and efficiency of the nRF52 Series devices. This integration ensures the longest battery life and the highest reliability for the end application. The synergy between the nRF52 Series and the Nordic PMICs highlights Nordic Semiconductor's commitment to providing a complete and cohesive solution for their customers' needs in wireless technology applications.