The SPI master can communicate with multiple slaves using individual chip select signals for each of the slave devices attached to a bus.

Listed here are the main features for the SPIM

  • SPI mode 0-3
  • EasyDMA direct transfer to/from RAM for both SPI Slave and SPI Master
  • Individual selection of IO pin for each SPI signal
Figure 1. SPIM — SPI master with EasyDMA

SPIM — SPI master with EasyDMA

The SPIM does not implement support for chip select directly. Therefore, the CPU must use available GPIOs to select the correct slave and control this independently of the SPI master. The SPIM supports SPI modes 0 through 3. The CONFIG register allows setting CPOL and CPHA appropriately.

Table 1. SPI modes
Mode Clock polarity Clock phase
CPOL CPHA
SPI_MODE0 0 (Active High) 0 (Leading)
SPI_MODE1 0 (Active High) 1 (Trailing)
SPI_MODE2 1 (Active Low) 0 (Leading)
SPI_MODE3 1 (Active Low) 1 (Trailing)

SPI master transaction sequence

An SPI master transaction consists of a sequence started by the START task followed by a number of events, and finally the STOP task.

An SPI master transaction is started by triggering the START task. The ENDTX event will be generated when the transmitter has transmitted all bytes in the TXD buffer as specified in the TXD.MAXCNT register. The ENDRX event will be generated when the receiver has filled the RXD buffer, i.e. received the last possible byte as specified in the RXD.MAXCNT register.

Following a START task, the SPI master will generate an END event when both ENDRX and ENDTX have been generated.

The SPI master is stopped by triggering the STOP task. A STOPPED event is generated when the SPI master has stopped.

If the ENDRX event has not already been generated when the SPI master has come to a stop, the SPI master will generate the ENDRX event explicitly even though the RX buffer is not full.

If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have not been transmitted.

The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at the same time; this is illustrated in SPI master transaction.

Figure 2. SPI master transaction

SPI master transaction: START task, ENDTX, and ENDRX events

Master mode pin configuration

The SCK, MOSI, and MISO signals associated with the SPI master are mapped to physical pins according to the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.

The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI and PSEL.MISO must only be configured when the SPI master is disabled.

To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral as described in GPIO configuration prior to enabling the SPI. This configuration must be retained in the GPIO for the selected IOs as long as the SPI is enabled.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.

Table 2. GPIO configuration
SPI master signal SPI master pin Direction Output value
SCK As specified in PSEL.SCK Output Same as CONFIG.CPOL
MOSI As specified in PSEL.MOSI Output 0
MISO As specified in PSEL.MISO Input Not applicable

Shared resources

The SPI shares registers and other resources with other peripherals that have the same ID as the SPI. Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be configured and used.

Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates correctly.

See the Instantiation table in Instantiation for details on peripherals and their IDs.

EasyDMA

The SPIM implements EasyDMA for accessing RAM without CPU involvement.

The SPIM peripheral implements the following EasyDMA channels:
Table 3. SPIM EasyDMA Channels
Channel Type Register Cluster
TXD READER TXD
RXD WRITER RXD

For detailed information regarding the use of EasyDMA, see EasyDMA.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next transmission immediately after having received the STARTED event.

The SPI master will automatically stop transmitting after TXD.MAXCNT bytes have been transmitted and RXD.MAXCNT bytes have been received. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined in the ORC register. If TXD.MAXCNT is larger than RXD.MAXCNT, the superfluous received bytes will be discarded.

The ENDRX/ENDTX event indicate that EasyDMA has finished accessing respectively the RX/TX buffer in RAM. The END event gets generated when both RX and TX are finished accessing the buffers in RAM.

In the case of bus congestion as described in AHB multilayer interconnect, data loss may occur.

Low power

When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.

The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register.

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA

SPIM0 : S
SPIM0 : NS

0x50008000
0x40008000

 US NS SA No

SPI master 0

SPIM1 : S
SPIM1 : NS

0x50009000
0x40009000

 US NS SA No

SPI master 1

SPIM2 : S
SPIM2 : NS

0x5000A000
0x4000A000

 US NS SA No

SPI master 2

SPIM3 : S
SPIM3 : NS

0x5000B000
0x4000B000

 US NS SA No

SPI master 3

Register overview

Register Offset TZ Description
TASKS_START 0x010

Start SPI transaction
TASKS_STOP 0x014

Stop SPI transaction
TASKS_SUSPEND 0x01C

Suspend SPI transaction
TASKS_RESUME 0x020

Resume SPI transaction
SUBSCRIBE_START 0x090

Subscribe configuration for task START
SUBSCRIBE_STOP 0x094

Subscribe configuration for task STOP
SUBSCRIBE_SUSPEND 0x09C

Subscribe configuration for task SUSPEND
SUBSCRIBE_RESUME 0x0A0

Subscribe configuration for task RESUME
EVENTS_STOPPED 0x104

SPI transaction has stopped
EVENTS_ENDRX 0x110

End of RXD buffer reached
EVENTS_END 0x118

End of RXD buffer and TXD buffer reached
EVENTS_ENDTX 0x120

End of TXD buffer reached
EVENTS_STARTED 0x14C

Transaction started
PUBLISH_STOPPED 0x184

Publish configuration for event STOPPED
PUBLISH_ENDRX 0x190

Publish configuration for event ENDRX
PUBLISH_END 0x198

Publish configuration for event END
PUBLISH_ENDTX 0x1A0

Publish configuration for event ENDTX
PUBLISH_STARTED 0x1CC

Publish configuration for event STARTED
SHORTS 0x200

Shortcuts between local events and tasks
INTENSET 0x304

Enable interrupt
INTENCLR 0x308

Disable interrupt
ENABLE 0x500

Enable SPIM
PSEL.SCK 0x508

Pin select for SCK
PSEL.MOSI 0x50C

Pin select for MOSI signal
PSEL.MISO 0x510

Pin select for MISO signal
FREQUENCY 0x524

SPI frequency. Accuracy depends on the HFCLK source selected.
RXD.PTR 0x534

Data pointer
RXD.MAXCNT 0x538

Maximum number of bytes in receive buffer
RXD.AMOUNT 0x53C

Number of bytes transferred in the last transaction
RXD.LIST 0x540

EasyDMA list type
TXD.PTR 0x544

Data pointer
TXD.MAXCNT 0x548

Maximum number of bytes in transmit buffer
TXD.AMOUNT 0x54C

Number of bytes transferred in the last transaction
TXD.LIST 0x550

EasyDMA list type
CONFIG 0x554

Configuration register
ORC 0x5C0

Over-read character. Character clocked out in case an over-read of the TXD buffer.

TASKS_START

Address offset: 0x010

Start SPI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_START

Start SPI transaction

Trigger

1

Trigger task

TASKS_STOP

Address offset: 0x014

Stop SPI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_STOP

Stop SPI transaction

Trigger

1

Trigger task

TASKS_SUSPEND

Address offset: 0x01C

Suspend SPI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_SUSPEND

Suspend SPI transaction

Trigger

1

Trigger task

TASKS_RESUME

Address offset: 0x020

Resume SPI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_RESUME

Resume SPI transaction

Trigger

1

Trigger task

SUBSCRIBE_START

Address offset: 0x090

Subscribe configuration for task START

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that task START will subscribe to
B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

SUBSCRIBE_STOP

Address offset: 0x094

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that task STOP will subscribe to
B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

SUBSCRIBE_SUSPEND

Address offset: 0x09C

Subscribe configuration for task SUSPEND

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that task SUSPEND will subscribe to
B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

SUBSCRIBE_RESUME

Address offset: 0x0A0

Subscribe configuration for task RESUME

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that task RESUME will subscribe to
B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

EVENTS_STOPPED

Address offset: 0x104

SPI transaction has stopped

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENTS_STOPPED

SPI transaction has stopped

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_ENDRX

Address offset: 0x110

End of RXD buffer reached

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENTS_ENDRX

End of RXD buffer reached

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_END

Address offset: 0x118

End of RXD buffer and TXD buffer reached

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENTS_END

End of RXD buffer and TXD buffer reached

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_ENDTX

Address offset: 0x120

End of TXD buffer reached

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENTS_ENDTX

End of TXD buffer reached

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_STARTED

Address offset: 0x14C

Transaction started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENTS_STARTED

Transaction started

NotGenerated

0

Event not generated

Generated

1

Event generated

PUBLISH_STOPPED

Address offset: 0x184

Publish configuration for event STOPPED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that event STOPPED will publish to
B

RW

EN

Disabled

0

Disable publishing

Enabled

1

Enable publishing

PUBLISH_ENDRX

Address offset: 0x190

Publish configuration for event ENDRX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that event ENDRX will publish to
B

RW

EN

Disabled

0

Disable publishing

Enabled

1

Enable publishing

PUBLISH_END

Address offset: 0x198

Publish configuration for event END

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that event END will publish to
B

RW

EN

Disabled

0

Disable publishing

Enabled

1

Enable publishing

PUBLISH_ENDTX

Address offset: 0x1A0

Publish configuration for event ENDTX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that event ENDTX will publish to
B

RW

EN

Disabled

0

Disable publishing

Enabled

1

Enable publishing

PUBLISH_STARTED

Address offset: 0x1CC

Publish configuration for event STARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CHIDX

[0..255]

DPPI channel that event STARTED will publish to
B

RW

EN

Disabled

0

Disable publishing

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

END_START

Shortcut between event END and task START

Disabled

0

Disable shortcut

Enabled

1

Enable shortcut

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

STOPPED

Write '1' to enable interrupt for event STOPPED

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
B

RW

ENDRX

Write '1' to enable interrupt for event ENDRX

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
C

RW

END

Write '1' to enable interrupt for event END

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
D

RW

ENDTX

Write '1' to enable interrupt for event ENDTX

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
E

RW

STARTED

Write '1' to enable interrupt for event STARTED

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

STOPPED

Write '1' to disable interrupt for event STOPPED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
B

RW

ENDRX

Write '1' to disable interrupt for event ENDRX

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
C

RW

END

Write '1' to disable interrupt for event END

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
D

RW

ENDTX

Write '1' to disable interrupt for event ENDTX

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled
E

RW

STARTED

Write '1' to disable interrupt for event STARTED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

ENABLE

Address offset: 0x500

Enable SPIM

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ENABLE

Enable or disable SPIM

Disabled

0

Disable SPIM

Enabled

7

Enable SPIM

PSEL.SCK

Address offset: 0x508

Pin select for SCK

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

[0..31]

Pin number
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.MOSI

Address offset: 0x50C

Pin select for MOSI signal

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

[0..31]

Pin number
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.MISO

Address offset: 0x510

Pin select for MISO signal

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

[0..31]

Pin number
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

FREQUENCY

Address offset: 0x524

SPI frequency. Accuracy depends on the HFCLK source selected.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

FREQUENCY

SPI master data rate

K125

0x02000000

125 kbps

K250

0x04000000

250 kbps

K500

0x08000000

500 kbps

M1

0x10000000

1 Mbps

M2

0x20000000

2 Mbps

M4

0x40000000

4 Mbps

M8

0x80000000

8 Mbps

RXD

RXD EasyDMA channel

RXD.PTR

Address offset: 0x534

Data pointer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PTR

Data pointer

Note: See the memory chapter for details about which memories are available for EasyDMA.

RXD.MAXCNT

Address offset: 0x538

Maximum number of bytes in receive buffer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

MAXCNT

[1..0x1FFF]

Maximum number of bytes in receive buffer

RXD.AMOUNT

Address offset: 0x53C

Number of bytes transferred in the last transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

AMOUNT

[1..0x1FFF]

Number of bytes transferred in the last transaction

RXD.LIST

Address offset: 0x540

EasyDMA list type

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

LIST

List type

Disabled

0

Disable EasyDMA list

ArrayList

1

Use array list

TXD

TXD EasyDMA channel

TXD.PTR

Address offset: 0x544

Data pointer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PTR

Data pointer

Note: See the memory chapter for details about which memories are available for EasyDMA.

TXD.MAXCNT

Address offset: 0x548

Maximum number of bytes in transmit buffer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

MAXCNT

[1..0x1FFF]

Maximum number of bytes in transmit buffer

TXD.AMOUNT

Address offset: 0x54C

Number of bytes transferred in the last transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

AMOUNT

[1..0x1FFF]

Number of bytes transferred in the last transaction

TXD.LIST

Address offset: 0x550

EasyDMA list type

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

LIST

List type

Disabled

0

Disable EasyDMA list

ArrayList

1

Use array list

CONFIG

Address offset: 0x554

Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ORDER

Bit order

MsbFirst

0

Most significant bit shifted out first

LsbFirst

1

Least significant bit shifted out first
B

RW

CPHA

Serial clock (SCK) phase

Leading

0

Sample on leading edge of clock, shift serial data on trailing edge

Trailing

1

Sample on trailing edge of clock, shift serial data on leading edge
C

RW

CPOL

Serial clock (SCK) polarity

ActiveHigh

0

Active high

ActiveLow

1

Active low

ORC

Address offset: 0x5C0

Over-read character. Character clocked out in case an over-read of the TXD buffer.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ORC

Over-read character. Character clocked out in case an over-read of the TXD buffer.

Electrical specification

SPIM master interface electrical specifications

Symbol Description Min. Typ. Max. Units
fSPIM

Bit rates for SPIM1

 8 Mbps
tSPIM,START

Time from START task to transmission started

 1 µs

Serial Peripheral Interface Master (SPIM) timing specifications

Symbol Description Min. Typ. Max. Units
tSPIM,CSCK

SCK period

 125 ns
tSPIM,RSCK,LD

SCK rise time, standard drivea

 tRF,25pF
tSPIM,RSCK,HD

SCK rise time, high drivea

 tHRF,25pF
tSPIM,FSCK,LD

SCK fall time, standard drivea

 tRF,25pF
tSPIM,FSCK,HD

SCK fall time, high drivea

 tHRF,25pF
tSPIM,WHSCK

SCK high timea

 (0.5*tCSCK) – tRSCK
tSPIM,WLSCK

SCK low timea

 (0.5*tCSCK) – tFSCK
tSPIM,SUMI

MISO to CLK edge setup time

 19 ns
tSPIM,HMI

CLK edge to MISO hold time

 18 ns
tSPIM,VMO

CLK edge to MOSI valid

 59 ns
tSPIM,HMO

MOSI hold time after CLK edge

 20 ns
Figure 3. SPIM timing diagram

SPI master timing diagram

1 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
a At 25pF load, including GPIO pin capacitance, see GPIO spec.