The following application example uses nPM1304 and an nRF5x Bluetooth® Low Energy System on Chip (SoC). For other configurations, see Reference circuitry.

The example application is for a design with the following configuration and features:
  • BUCK, LOADSW, and LDO are in use
  • Host software controls the device through TWI, the interrupt on GPIO1, and RESET on the GPIO0 pin
  • Three LEDs available
  • Battery pack with NTC thermistor
  • Ship mode
  • Low battery indication LED

Schematic

Figure 1. Application example
LED0 LED1 LED2 SHPHLD C7 10µF C8 10µF C4 10µF SW1 SW2 PVSS1 PVSS1 PVSS2 L1 2.2µH L2 2.2µH PVSS2 Net tie Net tie C2 10µF C3 10µF VBAT J 1 NTC VSYS CC1 CC2 VBUSOUT RESET INT VLDO C9 10µF C10 10µF C 6 2.2µF C5 1.0µF P0.xx VD D D- VDDH VBUS D+ VSS P0.xx P0.xx P0.xx P0.xx P0.xx P0.xx P0.xx U2 nRF5x GND 1 IO1 2 VCC 4 IO2 3 D1 PRTR5V0U2X VBUS VBUS D- CC2 CC1 S h i e l d SBU1 SBU2 GND GND D- D+ D+ J1 USB-C 2.0 RESET INT VOUT1 SDA SCL GPIO2 GPIO3 GPIO4 VBUSIN D_N D_P VOUT2 LSOUT LD1 L0603R LD2 L0603G LD3 L0603Y VSYS SW2 C13 100nF VSYS VOUT2 VSET1 VSET2 SW1 S DA SCL R3 4 7 k R4 1 5 0 k VB US 21 VSYS 20 VBAT 19 AVSS 33 VBUSOUT 22 LED0 25 LED1 26 LED2 27 CC1 23 CC2 24 NTC 18 SHPHLD 15 GPIO0 7 GPIO1 8 GPIO2 9 GPIO3 10 GPIO4 11 VDDIO 12 SCL 14 SDA 13 PVDD 4 SW1 3 VOUT1 1 VSET1 17 SW2 5 VOUT2 32 VSET2 16 PVSS1 2 PVSS2 6 VINLDO1 28 VOUTLDO1 29 LSIN2 30 LSOUT2 31 B U C K 1 B U C K 2 U1 nPM1304-QEAA C1 1.0µF C14 1.0µF C15 100nF

Supplying from BUCK

An application must not be supplied directly from VBAT. This can interrupt the battery charging process causing unwanted behavior from the charger. Use either VOUT1, VOUT2, or VSYS to supply the application.

BUCK1 starts automatically and supplies the nRF5x host SoC with 1.8 V. BUCK1 is the I/O voltage for the system. BUCK2 starts automatically with 3 V output voltage for other application features.

USB port negotiation

nRF5x can connect to a USB host.

Port negotiation is performed after nPM1304 port detection. The nRF5x device and nPM1304 are both connected to USB-C in the application example.
  • The D+ and D- pins are connected to nRF5x. The CC1 and CC2 pins are connected to nPM1304. The nRF5x SoC must wait until nPM1304 completes port detection using the USB configuration channel.
  • The nRF5x device must set the correct current limit as described in Charge current limit (ICHG).
  • VBUS is supplied to SYSREG on nPM1304 and VBUSOUT supplies the nRF5x VBUS input.
VBUSOUT is only for host sensing and should not be used as a source.

Charging and error states

Three LEDs can be used for charging indicators or general purpose by the application.

Termination voltage and current

The termination voltage, VTERM, is configured through TWI up to 4.65 V.

Charge current is configured through TWI.

NTC thermistor configuration

The NTC pin connects to an external NTC thermistor. Place the NTC thermistor with thermal coupling on the battery pack.

Ship mode

Ship mode is enabled at production time through the TWI interface.

SHPHLD is connected to SW2 and is in the circuit to exit Ship mode. If another circuit is present instead of a button, any signal that is able to pull the SHPHLD pin low for the required period can be connected to that net. See Ship and Hibernate modes for more information.