Access to the nRF54L15 SoC GPIOs is available from headers P0, P1, and P2.
The P6 header and P4 test points provide access to ground and power on the nRF54L15 DK.
Figure 1. nRF54L15 DK GPIO headers
Pin maps
| P0 signal | Function | Default connected on P0 |
|---|---|---|
| P0.00 | UART0_TXD | Yes |
| P0.01 | UART0_RXD | Yes |
| P0.02 | UART0_RST | Yes |
| P0.03 | UART0_CST | Yes |
| P0.04 | Button 3 | Yes |
| P1 signal | Function | Default connected on P1 |
|---|---|---|
| P1.00 | 32.768 kHz, XL1 | No. Solder bridges must be configured. |
| P1.01 | 32.768 kHz, XL2 | No. Solder bridges must be configured. |
| P1.02 | NFC1 | No. 0R resistors must be configured. |
| P1.03 | NFC2 | No. 0R resistors must be configured. |
| P1.04 | UART1_TXD | Yes. |
| P1.05 | UART1_RXD | Yes. |
| P1.06 | UART1_RST | Yes. |
| P1.07 | UART1_CTS | Yes. |
| P1.08 | Button 2 | Yes. |
| P1.09 | Button 1 | Yes. |
| P1.10 | LED 1 | Yes. |
| P1.11 | Yes. | |
| P1.12 | Yes. | |
| P1.13 | Button 0 | Yes. |
| P1.14 | LED 3 | Yes. |
| P2 signal | Function | Default connected on P2 |
|---|---|---|
| P2.00 | SPI_IO3/External flash | No. Board Configurator must be used. |
| P2.01 | SPI_CLK/External flash | No. Board Configurator must be used. |
| P2.02 | SPI_IO0/External flash | No. Board Configurator must be used. |
| P2.03 | SPI_IO2/External flash | No. Board Configurator must be used. |
| P2.04 | SPI_IO1/External flash | No. Board Configurator must be used. |
| P2.05 | SPI_CS/External flash | No. Board Configurator must be used. |
| P2.06 | Trace CLK | Yes. |
| P2.07 | Trace [0]/LED 2 | Yes. |
| P2.08 | Trace [1] | Yes. |
| P2.09 | Trace [2]/LED 0 | Yes. |
| P2.10 | Trace [3] | Yes. |
Headers P30, P31, and P32 are power supply pins that each provide 5.0 V for expansion boards connected to GPIO ports.
| P30, P31, P32 signal | Function |
|---|---|
| 1 | P5V0 from PMIC |
| 2 | Ground |
| 3 | Do not connect |
| 4 | Ground |