Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files, can be downloaded from www.nordicsemi.com.

The following reference circuits for nPM1304 show the schematics and components to support different configurations in a design.

Table 1. PCB application configuration
Configuration 1 Configuration 2 Configuration 3
Description Full configuration Simple configuration Minimal configuration
BUCKs Both configured One configured Not used
LOADSWs Both configured, LDO mode One configured, load switch mode Not used
Ship mode exit Configured Configured Not used
Charging Available Available Available
Battery thermistor Configured Configured Not used
LEDs Three available One available Not used
GPIOs Configured Configured Configured
TWI Configured Configured Configured
VSET1 47 kΩ 47 kΩ Not used
VSET2 150 kΩ Not used Not used
VOUT1 1.8 V 1.8 V Not used
VOUT2 3.0 V Not used Not used
VBUSOUT Configured Configured Not used
VDDIO Configured Configured Configured

Configuration 1

Figure 1. QFN schematic
LED0 LED1 LED2 SHPHLD C7 10µF C8 10µF VSET1 SW1 SW2 VSET2 L1 2.2µH L2 2.2µH C13 100nF C1 1.0µF VBAT J1 Battery pack VDDIO NTC VOUT2 VBUSIN CC1 CC2 SDA SCL GPIO2 GPIO3 GPIO4 VOUT1 R3 4 7 k R4 1 5 0 k Optional LEDs R1 1 0 k R2 1 0 k VOUTLDO1 VOUTLDO2 C9 10µF C10 10µF C11 10µF C12 10µF C6 2.2µF Optional TWI pull-up resistors R G B LD1 VSYS GPIO0 GPIO1 VINLDO1 VINLDO2 PVSS1 PVSS2 Via to GND-layer on PVSS1 Via to GND-layer on PVSS2 Net tie Net tie VBUS 21 VSYS 20 VBAT 19 AVSS 33 VBUSOUT 22 LED0 25 LED1 26 LED2 27 CC1 23 CC2 24 NTC 18 SHPHLD 15 GPIO0 7 GPIO1 8 GPIO2 9 GPIO3 10 GPIO4 11 VDDIO 12 SCL 14 SDA 13 PVDD 4 SW1 3 VOUT1 1 VSET1 17 SW2 5 VOUT2 32 VSET2 16 PVSS1 2 PVSS2 6 LSIN1/VINLDO1 28 LSOUT1/VOUTLDO1 29 LSIN2/VINLDO2 30 LSOUT2/VOUTLDO2 31 B U C K 1 B U C K 2 U1 nPM1304-QEAA C4 10µF C2 10µF C3 10µF VSYS VBUSOUT C5 1.0µF PVSS1 PVSS2
Figure 2. CSP schematic
LED0 LED1 LED2 SHPHLD C7 10µF C8 10µF VSET1 C4 10µF SW1 SW2 VSET2 PVSS1 PVSS1 PVSS2 L1 2.2µH L2 2.2µH PVSS2 C13 100nF C1 1.0µF C2 10µF C3 10µF VBAT J1 Battery pack VDDIO NTC VSYS VOUT2 VBUSIN CC1 CC2 SDA SCL VBUSOUT GPIO2 GPIO3 VOUT1 R3 4 7 k R4 1 5 0 k Optional LEDs R1 1 0 k R2 1 0 k VOUTLDO1 VOUTLDO2 C9 10µF C10 10µF C11 10µF C12 10µF C6 2.2µF C5 1.0µF Optional TWI pull-up resistors R G B LD1 VSYS GPIO0 GPIO1 VINLDO1 VINLDO2 Via to GND-layer on PVSS1 Via to GND-layer on PVSS2 Net tie Net tie VBUS B1 VSYS C2 VBAT D2 AVSS A6 VBUSOUT C3 LED0 A1 LED1 A2 LED2 A3 CC1 D5 CC2 B3 NTC D3 SHPHLD D4 GPIO0 D6 GPIO1 E6 GPIO2 C5 GPIO3 C4 VDDIO E4 SCL E3 SDA E5 PVDD C7 SW1 B7 VOUT1 B6 VSET1 E2 SW2 D7 VOUT2 C6 VSET2 E1 PVSS1 A7 PVSS2 E7 LSIN1/VINLDO1 B4 LSOUT1/VOUTLDO1 A4 LSIN2/VINLDO2 B5 LSOUT2/VOUTLDO2 A5 VBUS B2 VSYS C1 VBAT D1 B U C K 1 B U C K 2 U1 nPM1304-CAAA
Table 2. Bill of material
Designator Value Description Package
C1 1.0 μF Capacitor, X5R, 25 V, ±10% 0603
C5 1.0 μF Capacitor, X5R, 10 V, ±10% 0603
C2, C3, C4, C7, C8, C9, C10, C11, C12 10 μF Capacitor, X5R, 16 V, ±20% 0603
C6 2.2 μF Capacitor, X5R, 10 V, ±10% 0603
C13 100 nF Capacitor, X5R 0201
L1, L2 2.2 μH Inductor, DCR < 400 mΩ, ±20% 0806
R1, R2 Dependent on bus speed and parasitic capacitances Optional pull-up resistors for TWI 0201
R3, R4 See Output voltage selection Resistors for setting the BUCK1 and BUCK2 output voltages, ±5% 0201
U1 nPM1304 nPM1304 QFN32 or CSP35

Configuration 2

Figure 3. QFN schematic
LED0C710µFVSET1C410µFSW1PVSS1PVSS1L12.2µHC13100nFC11.0µFC210µFVBATJ1Battery packVDDIONTCVSYSVBUSINCC1CC2VSYSGPIO2GPIO3GPIO4GPIO0VOUT1C62.2µFOptional TWI pull-up resistorsVSYSLSOUT1Optional LEDSHPHLDR110kR210kSDASCLC51.0µFVBUSOUTC141.0µFGPIO1VOUT1R347kVia to GND-layer on PVSS1Net tieVBUS21VSYS20VBAT19AVSS33VBUSOUT22LED025LED126LED227CC123CC224NTC18SHPHLD15GPIO07GPIO18GPIO29GPIO310GPIO411VDDIO12SCL14SDA13PVDD4SW13VOUT11VSET117SW25VOUT232VSET216PVSS12PVSS26LSIN1/VINLDO128LSOUT1/VOUTLDO129LSIN2/VINLDO230LSOUT2/VOUTLDO231BUCK1BUCK2U1nPM1304-QEAALD1L0603G
Figure 4. CSP schematic
LED0C710µFVSET1C410µFSW1PVSS1PVSS1L12.2µHC13100nFC210µFVBATJ1Battery packVDDIONTCVSYSVBUSINCC1CC2VSYSGPIO2GPIO3GPIO0VOUT1R347kC62.2µFOptional TWI pull-up resistorsVSYSLD1L0603GLSOUT1Optional LEDSHPHLDR110kR210kSDASCLC51.0µFVBUSOUTC141.0µFGPIO1VOUT1Via to GND-layer on PVSS1Net tieVBUSB1VSYSC2VBATD2AVSSA6VBUSOUTC3LED0A1LED1A2LED2A3CC1D5CC2B3NTCD3SHPHLDD4GPIO0D6GPIO1E6GPIO2C5GPIO3C4VDDIOE4SCLE3SDAE5PVDDC7SW1B7VOUT1B6VSET1E2SW2D7VOUT2C6VSET2E1PVSS1A7PVSS2E7LSIN1/VINLDO1B4LSOUT1/VOUTLDO1A4LSIN2/VINLDO2B5LSOUT2/VOUTLDO2A5VBUSB2VSYSC1VBATD1BUCK1BUCK2U1nPM1304-CAAAC11.0µF
Table 3. Bill of material
Designator Value Description Package
C1 1.0 μF Capacitor, X5R, 25 V, ±10% 0603
C5, C14 1.0 μF Capacitor, X5R, 10 V, ±10% 0603
C2, C4, C7 10 μF Capacitor, X5R, 16 V, ±20% 0603
C6 2.2 μF Capacitor, X5R, 10 V, ±10% 0603
C13 100 nF Capacitor, X5R 0201
L1 2.2 μH Inductor, DCR < 400 mΩ, ±20% 0806
R1, R2 Dependent on bus speed and parasitic capacitances Optional pull-up resistors for TWI 0201
R3 See Output voltage selection Resistor for setting the BUCK1 output voltage, ±5% 0201
U1 nPM1304 nPM1304 QFN32 or CSP35

Configuration 3

Figure 5. QFN schematic
C410µFC13100nFC11.0µFVBATVDDIOVSYSVBUSINCC1CC2C62.2µFJ1Battery packR110kR210kSDASCLOptional TWI pull-up resistorsC51.0µFGPIO2GPIO3GPIO4GPIO0GPIO1VBUS21VSYS20VBAT19AVSS33VBUSOUT22LED025LED126LED227CC123CC224NTC18SHPHLD15GPIO07GPIO18GPIO29GPIO310GPIO411VDDIO12SCL14SDA13PVDD4SW13VOUT11VSET117SW25VOUT232VSET216PVSS12PVSS26LSIN1/VINLDO128LSOUT1/VOUTLDO129LSIN2/VINLDO230LSOUT2/VOUTLDO231BUCK1BUCK2U1nPM1304-QEAA
Figure 6. CSP schematic
C410µFC13100nFVBATVDDIOVSYSVBUSINCC1CC2SDASCLGPIO2GPIO3R110kR210kC62.2µFC51.0µFOptional TWI pull-up resistorsGPIO0GPIO1J1Battery packC11.0µFVBUSB1VSYSC2VBATD2AVSSA6VBUSOUTC3LED0A1LED1A2LED2A3CC1D5CC2B3NTCD3SHPHLDD4GPIO0D6GPIO1E6GPIO2C5GPIO3C4VDDIOE4SCLE3SDAE5PVDDC7SW1B7VOUT1B6VSET1E2SW2D7VOUT2C6VSET2E1PVSS1A7PVSS2E7LSIN1/VINLDO1B4LSOUT1/VOUTLDO1A4LSIN2/VINLDO2B5LSOUT2/VOUTLDO2A5VBUSB2VSYSC1VBATD1BUCK1BUCK2U1nPM1304-CAAA
Table 4. Bill of material
Designator Value Description Package
C1 1.0 μF Capacitor, X5R, 25 V, ±10% 0603
C5 1.0 μF Capacitor, X5R, 10 V, ±10% 0603
C4 10 μF Capacitor, X5R, 10 V, ±20% 0603
C6 2.2 μF Capacitor, X5R, 10 V, ±10% 0603
C13 100 nF Capacitor, X5R 0201
R1, R2 Dependent on bus speed and parasitic capacitances Optional pull-up resistors for TWI 0201
U1 nPM1304 nPM1304 QFN32 or CSP35

PCB guidelines

A well designed PCB is necessary to achieve good performance. A poor layout can lead to loss in performance or functionality.

To ensure functionality, it is essential to follow the schematics and layout references closely.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance.

The BUCK supply voltage should be decoupled with high performance capacitors as close as possible to the supply pins.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the device.

PCB layout example

The PCB layouts for configuration 1 are shown here for QFN followed by CSP.

QFN PCB layout

For all available reference layouts, see the Reference Layout section on the Downloads tab for nPM1304 on www.nordicsemi.com.

Figure 7. Top silkscreen layer QFN
top silk layer
Figure 8. Top layer QFN
top layer
Figure 9. Mid layer 1 QFN
mid layer 1
Figure 10. Mid layer 2 QFN
mid layer 2
Figure 11. Bottom layer QFN
bottom layer
Note: No components on the bottom layer.

CSP PCB layout

Figure 12. Top silkscreen layer CSP
top silk layer
Figure 13. Top layer CSP
top layer
Figure 14. Mid layer 1 CSP
mid layer 1
Figure 15. Mid layer 2 CSP
mid layer 2
Figure 16. Mid layer 3 CSP
mid layer 2
Figure 17. Mid layer 4 CSP
mid layer 4
Figure 18. Bottom layer CSP
bottom layer
Note: No components are on the bottom layer.