ANT (pin 35) is a 50 Ω single-end interface for the Long-Term Evolution (LTE) and DECT NR+ antenna. To ensure best performance, antenna impedance and the characteristic impedance of the transmission line connecting the antenna to the ANT pin must be 50 Ω.
Impedance mismatch leads to performance degradation. However, nRF9151 typically remains 3GPP compatible with a VSWR of up to 3:1 in most test cases. For more information, see Transmitter performance at load VSWR 3:1.
Keep the length of the transmission line from the antenna to the ANT pin as short as possible. This reduces power deterioration in transmission and reception for nRF9151 which improves power consumption and network coverage. A maximum of 0.5 dB loss in the transmission line is acceptable.
nRF9151 includes an Electrostatic Discharge (ESD) circuit on the ANT pin. Additional ESD protection is recommended, especially if there are active components, such as switches or antenna tuners, in the antenna path. For the ESD requirements, see the component datasheets. For the nRF9151 ESD ratings, see nRF9151 Product Specification.
The ANT pin is DC grounded. A matching network of a minimum of three components is typically needed close to the antenna. The component values and matching topology depend on the antenna application and antenna path impedance and need to be optimized individually for each design.
For more information on the antenna interface, see nRF91 Series Antenna and RF Interface Guidelines.
PCB layout design
When designing the PCB layout, consider the following recommendations for the ANT pin:
- To ensure good radiated performance, begin the design by locating the LTE and DECT NR+ antenna on the PCB.
- Ensure preliminary antenna performance on a chosen PCB location, for example, by simulation.
- When multiple antennas, for example, LTE, Global Navigation Satellite System (GNSS), and Bluetooth® Low Energy are present, minimize antenna crosstalk.
- Antenna transmission line impedance should be 50 Ω. Take this into account when selecting the PCB stack-up.
- Avoid excessive capacitance in routing by opening ground layers under component pads. For example, if the routing is on the top PCB layer, open the ground plane under the ANT pad on the next metal layer.
- When opening ground planes, avoid exposing noisy routings under the ANT pad.
- Favor routing in shielded PCB layers to minimize radiated noise coupling to the ANT line.
- Avoid long routing because it causes excessive insertion loss which deteriorates RF performance.
- Ensure a continuous reference ground plane above, below, or both of the ANT routing.
- Consider adding a test connector to the antenna path for production test and diagnostic purposes. Ensure that the test connector or solution does not deteriorate the impedance of the transmission line.