COEX

The COEX interface consists of pins 52–54. It is dedicated for RF interference avoidance towards a companion radio device, such as an external positioning device or Bluetooth® Low Energy device.

The COEX interface is powered from VDD_GPIO. To control the COEX interface, the LTE modem must be active. When the LTE modem is not active, the COEX interface floats. Therefore, it is mandatory to use external pull-down resistors in the size range of 100 kΩ in the COEX interface.

The COEX pins have the following functionalities:

• COEX0 (pin 52)
  • Can be configured for external Global Navigation Satellite System (GNSS) Low-Noise Amplifier (LNA) control (active high) during GNSS receive the same way as the %XMAGPIO command with the exception that %XCOEX0 controls only one pin. For more information, see COEX0 pin control configuration %XCOEX0 in nRF91x1 Cellular AT Commands Reference Guide.
  Note: When using DECT NR+, the COEX0 signal must be accessible through a test point or similar on the application board to enable DECT NR+ regulatory measurement capability.
  Note: Load capacitance, including parasitic routing capacitance, must not exceed 50 pF.
• COEX1 (pin 53)
  • Can be used during GNSS receive to deliver GNSS one Pulse Per Second (1PPS) time mark pulse.
• COEX2 (pin 54)
  • Can be used as an indicator of LTE or GNSS RF activity from the modem to an external device. When COEX2 is high, the LTE or GNSS RF is active, and when it is low, the LTE or GNSS RF is inactive.
  • Can be used as a “BLE nGrant”. This means that Bluetooth Low Energy should not transmit when COEX2 is high and Bluetooth Low Energy can transmit when COEX2 is low.
  • Can be used with %XRFTEST AT commands. For more information, see Production test features in nRF91x1 Cellular AT Commands Reference Guide.
    Note: When using DECT NR+, the COEX2 signal must be accessible through a test point or similar on the application board to enable DECT NR+ regulatory measurement capability.
    Note: Load capacitance, including parasitic routing capacitance, must not exceed 50 pF.

The COEX pins are powered from VDD_GPIO (pin 65). They have the same voltage level as VDD_GPIO and any unwanted noise or spurious that VDD_GPIO might contain. Therefore, proper noise filtering in VDD_GPIO is important. It is also important for each individual COEX pin to meet the filtering requirements specified for the peripherals connected to them.

To reduce transient currents, series resistors or ferrite beads can be used in the COEX lines. For low current, digital control type of COEX routings, resistor values in the range of 100 Ω to 1 kΩ can be considered. However, the optimal resistor values depend mainly on the connected peripheral drive currents and communication speed required by the peripherals.

In addition to the series resistor, bypass capacitors in the range of a few pF can be considered. They can help to reduce RF coupling to the COEX lines. Unused COEX pins can be left unconnected electrically, but it is recommended to connect them to the application board for improved thermal and mechanical performance. For more information on the COEX interface configurations, see nRF9151 Product Specification.