When designing a PCB, follow the guidelines for an improved current loop design.
To reduce the loop antenna area that emits Electromagnetic Interference (EMI), minimize the buck regulator's current loop area. Place components as close as possible to the PVDD, PVSS1/2, and SW1/2 pins.
Visualize both switching cycles and how the current flows in both cycles on the PCB, including the ground plane. The current should ideally rotate in the same direction in both switching cycles as shown in Buck regulator switching cycles. This minimizes the change in magnetic field and therefore EMI.
Some inductors have a dot showing the direction of rotation around the core. If possible, place the inductor so that the direction of current follows the rotation of the main current loop. In some cases, a current direction change cannot be avoided.
When placing components and minimizing current loops, pay attention to input and output capacitor grounds and their position. The grounds should be close to each other and, if possible, on the same copper area on the top layer and strongly connected to the ground plane. This automatically minimizes the loops.
At low frequencies, the current flows in the path of least resistance, which is typically the shortest path, but at high frequencies the current follows the path of least inductance. This means that at high frequency the return current in the ground plane goes through the path that creates the smallest loop area. In the ground plane this path is right under the positive current on the top layer. Keep the ground plane intact in this area. The following figure shows the current path at low and high frequencies and the area which is marked in grey color where the ground layer should be kept intact.
Consider the following guidelines for the ground layer:
- Keep the ground plane intact.
- A solid ground plane as the second layer is critical. Any traces or routes here are likely to increase the high current loop area and cause issues with EMI, EMC, or radio sensitivity.
- If routing on the ground plane is unavoidable, limit routing directly under the Power Management Integrated Circuit (PMIC) to short escape routing and change layer as soon as possible. Do not route under the high current paths on top.
- Distance to the ground plane affects the current loop area. Therefore, it is recommended to use the second layer for ground. Also, using thinner prepreg reduces the loop area.