Use the standard Serial Wire Debug (SWD) Arm® CoreSight™ Debug Access Port (DAP) protocol to write data into the non-volatile memory (RRAM).
Different nRF54L Series devices have different base address for the Resistive Random-Access Memory Controller (RRAMC). The following table lists the addresses for the different devices.
| Register name | nRF54L05, nRF54L10, nRF54L15 | nRF54LM20A, nRF54LM20B, nRF54LV10A | nRF54LS05A, nRF54LS05B |
|---|---|---|---|
| RRAMC.TASKS_COMMITWRITEBUF | 0x5004B008 | 0x5004E008 | 0x4004E008 |
| RRAMC.CONFIG | 0x5004B500 | 0x5004E500 | 0x4004E500 |
| RRAMC.READY | 0x5004B400 | 0x5004E400 | 0x4004E400 |
The RRAM controller has different write buffer sizes. The following table lists the maximum write buffer size, the corresponding data chunk size, and the corresponding RRAMC.CONFIG register value for the configuration.
| Device | Write buffer size in bytes | RRAM data unit size in bytes | Chunk size in bytes | CONFIG register value |
|---|---|---|---|---|
| nRF54LV10A | 16 | 16 | 256 | 0x1001 |
| nRF54L05, nRF54L10, nRF54L15, nRF54LM20A, nRF54LM20B | 32 | 16 | 512 | 0x2001 |
| nRF54LS05A, nRF54LS05B | 32 | 8 | 256 | 0x2001 |
Complete the following steps:
The ranges of writeable addresses are the following:
- User Information Configuration Registers (UICR) addresses, located in addresses 0x00FFD000 through 0x00FFDFFC
- All program memory, located in addresses 0x00000000 through ((FICR.INFO.RRAM * 1024) – 4)