[7] UICR: Wrong code memory Read or Write after accessing UICR

nRF9161 Revision 1 Errata

This anomaly applies to Revision 1, build codes LACA-A0A.

It was inherited from the previous IC revision Engineering A.

Symptoms

The read or write operation to the code memory uses the value previously read from or written to UICR.

Conditions

Two consecutive CPU read or write operations to the flash are executed. The first read or write is to UICR, and the second read or write is to the code memory area due to software execution or interrupt handling.

Consequences

Reading or writing the code memory uses values from the UICR operation.

Workaround

Apply the following workaround:

  • Add a Data Synchronization Barrier (DSB) operation between the two consecutive CPU read or write operations when the first read or write is to UICR and the second is to the code memory area.
  • Disable IRQs when accessing UICR.

Implement one of the following options:

In nrfx released with nRF Connect SDK v2.5.0 and later, this can be achieved by calling nrfx_nvmc_uicr_word_read:


    uint32_t a = nrfx_nvmc_uicr_word_read(&UICR_S->SOMEREGISTER);
    uint32_t b = *((uint32_t *)SOMEFLASHADDR);
    
Without nrfx, this can be achieved by implementing the procedure manually:

   bool irq_disabled = __get_PRIMASK() == 1;
   if (!irq_disabled){
	__disable_irq();
   }
   uint32_t value = UICR_S->SOMEREGISTER;
   __DSB();
   if(!irq_disabled){
	__enable_irq();
   }
   uint32_t b = *((uint32_t *)SOMEFLASHADDR);