This anomaly applies to Revision 2, build code CAAA-Bxx.
It was inherited from the previous SoC revision Revision 1.
Symptoms
A bit in the LATCH register reads '1' even after clearing it by writing '1'.
Conditions
Reading the LATCH register right after writing to it.
Consequences
Old value of the LATCH register is read.
Workaround
Have at least 3 CPU cycles of delay between the write and the subsequent read to the LATCH register. This can be achieved by having 3 dummy reads to the LATCH register.