The power-fail comparator (POF) provides the host with an early warning of an impending power supply failure.

POF is generated from an always active comparator monitoring the voltage on the VSYS pin. It can be configured through POFCONFIG to give a warning through a GPIO to the host.

If voltage on the VSYS pin drops below VSYSPOF, but voltage remains above the respective BOR threshold on the VBAT or VBUS pins, the VSYS pin is disabled after tPOFWAIT and registers are reset after tPWRDN. If VSYS > VSYSPOF, the chip powers up after tPWRDN. See Power fail warning.

Note: Before setting VSYSPOF, voltage on the VSYS pin must be higher than the selected threshold or it triggers a POF event and resets the device. The POF threshold is also reset to the default setting. VSYSPOF must be set to a higher voltage than the battery undervoltage protection level to avoid triggering the protection circuit. When VSYS > VSYSPOF, BUCK may start up again depending on VSET[n] pin configuration.

If configured, a power failure warning is issued in the following cases:

  • VBUS is removed while the battery is empty or not connected (VBAT < VSYSPOF)
  • VBUS rises above VBUSOVP while the battery is empty or not connected (VBAT < VSYSPOF)
  • The battery is removed when VBUS is not connected
  • The battery discharges until VBAT < VSYSPOF and VBUS is not connected
  • Battery voltage drops momentarily below VSYSPOF and VBUS is not connected
Figure 1. Power fail warning
Power fail warning
Figure 2. Power removal
Page-1 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 VSYS VSYS Sheet.12 LSOUT[n] (LOADSW) LSOUT[n] (LOADSW) Sheet.13 VOUT[n] (BUCK) VOUT[n] (BUCK) Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 VSYS drops down VSYS drops down Sheet.28 Normal Normal Sheet.29 No supply No supply Sheet.30 No act. cap disch. No act. cap disch. Sheet.31 Device internal reset by VBATBOR/VBUSBOR Device internal reset by VBATBOR/VBUSBOR Sheet.33 Sheet.34 Sheet.35 Input, pull-down Input, pull-down Sheet.36 Sheet.37 tPOFWAIT tPOFWAIT Sheet.38 No VBAT or VBUS No VBAT or VBUS Sheet.39 POF (GPIO) POF (GPIO) Sheet.40 Sheet.41 VBUSOUT VBUSOUT Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46

To use the POF warning feature, set POFWARNPOLARITY and POFENA to 1 in register POFCONFIG. GPIO settings are located in GPIO — General purpose input/output.

Electrical specification

Table 1. POF electrical specification
Symbol Description Min. Typ. Max. Unit
POF

VSYSPOF rising threshold, default

Always 100 mV (typ.) above the falling threshold

 2.8 V
VSYSPOF Minimum setting VSYSPOF falling threshold 2.5 V
VSYSPOF Default setting VSYSPOF falling threshold 2.7 V
VSYSPOF Maximum setting VSYSPOF falling threshold 3.4 V
tPOF Reaction time (from crossing the threshold to edge on the warning signal) 1 ms
tPWRDN Time in power-down mode 100 ms
tPOFWAIT Delay before enabling the active output capacitor discharge and disconnecting VBAT and VBUS from VSYS 30 ms

Registers

Instances

Instance Base address Description
POF 0x00000900

POF registers

POF register map

Register overview

Register Offset Description
POFCONFIG 0x0

Configuration for power failure

POFCONFIG

Address offset: 0x0

Configuration for power failure

Bit number 7 6 5 4 3 2 1 0
ID C C C C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

POFENA

Enable power failure warning

OFF

0

Warning disabled

ENABLED

1

Warning enabled
B

RW

POFWARNPOLARITY

Power failure warning polarity

LOACTIVE

0

Active low

HIACTIVE

1

Active high
C

RW

POFVSYSTHRESHSEL

Power failure threshold select

2V8

0

2.8 V

2V6

1

2.6 V

2V7

2

2.7 V

2V9

3

2.9 V

3V0

4

3.0 V

3V1

5

3.1 V

3V2

6

3.2 V

3V3

7

3.3 V

3V4

8

3.4 V

3V5

9

3.5 V

unused10

10

2.8 V

unused11

11

2.8 V

unused12

12

2.8 V

unused13

13

2.8 V

unused14

14

2.8 V

unused15

15

2.8 V