The device behavior when in specific operation modes and states is shown in the following diagram.
Active mode
PG/RESET is set HIGH unless the Reset button is pulling it LOW.
Ship, Hibernate, and Hibernate_PT modes can be entered through TWI and register bits.
The chip enters the Ship mode when pressing and holding the Ship button for 2 seconds.
A reset is initiated by pressing and holding the Reset button for tRST_DEB_L seconds (default 10 s). This forces the device to enter the Power cycle mode. A watchdog reset takes the chip to WD RESET state.
A BOOST overcurrent event sets the chip to the Power cycle mode.
Die temperature rising over TSDSD sets the chip to the COLD START state.
Hibernate mode
VOUT is discharged to ground. VINT remains supplied as BOOST is running in Ultra-Low Power mode. LDOSW can be configured to be ON in Ultra-Low Power mode. If enabled, the wakeup timer is running. PG/RESET is set LOW.
The SHPHLD pin and TIMER can set the chip to the WAKE UP state.
Please refer to Hibernate mode for more details.
Hibernate_PT mode
VOUT is discharged to ground. BOOST is in Pass-through mode so that VINT remains at VBAT level. LDOSW is OFF. If enabled, the wakeup timer is running. PG/RESET is set LOW.
A wakeup from the SHPHLD pin or TIMER causes the chip to enter the COLD START state and resets the registers.
Please refer to Hibernate mode for more details.
Ship mode
Everything is disabled and only the SHPHLD pin can wake up the chip.
Please refer to Ship mode for more details.
Power Cycle mode
BOOST and LDOSW are disabled in Power cycle mode. VOUT and LSOUT/VOUTLDO are discharged to ground and PG/RESET is set LOW. The registers will be reset.
When a delay of tPWRDN occurs, the chip returns to Active mode.