This anomaly applies to Revision 2, build codes QFAA-C00, CAAA-C00, QDAA-C00, QGAA-C00.
It was inherited from the previous SoC revision Revision 1.
Symptoms
Bus error responses during hibernate save are ignored.
Conditions
A bus fault occurs during the hibernate save sequence.
Consequences
The VPR CPU behavior is undefined.
Workaround
Before entering the lowest power state on VPR, ensure that the VPR context save memory register (VPRSAVEADDR) is set to memory address accessible to VPR.