Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration.

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA
FICR 0x00FF0000 HF S NA No

Factory information configuration

Register overview

Register Offset TZ Description
SIPINFO.PARTNO 0x140

SIP part number
SIPINFO.HWREVISION[n] 0x144

SIP hardware revision, encoded in ASCII, for example B0A or B1A
SIPINFO.VARIANT[n] 0x148

SIP VARIANT, encoded in ASCII, for example LACA. See Ordering information for details.
INFO.DEVICEID[n] 0x204

Device identifier
INFO.RAM 0x218

RAM variant
INFO.FLASH 0x21C

Flash variant
INFO.CODEPAGESIZE 0x220

Code memory page size
INFO.CODESIZE 0x224

Code memory size
INFO.DEVICETYPE 0x228

Device type
TRIMCNF[n].ADDR 0x300

Address
TRIMCNF[n].DATA 0x304

Data
TRNG90B.BYTES 0xC00

Amount of bytes for the required entropy bits
TRNG90B.RCCUTOFF 0xC04

Repetition counter cutoff
TRNG90B.APCUTOFF 0xC08

Adaptive proportion cutoff
TRNG90B.STARTUP 0xC0C

Amount of bytes for the startup tests
TRNG90B.ROSC1 0xC10

Sample count for ring oscillator configuration 1
TRNG90B.ROSC2 0xC14

Sample count for ring oscillator configuration 2
TRNG90B.ROSC3 0xC18

Sample count for ring oscillator configuration 3
TRNG90B.ROSC4 0xC1C

Sample count for ring oscillator configuration 4

SIPINFO

SIP-specific device information is provided in the following chapters.

SIPINFO.PARTNO

Address offset: 0x140

SIP part number

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

PARTNO

9161

0x00009161

Device is an nRF9161 sip

9160

0x00009160

Device is an nRF9160 sip

9151

0x00009151

Device is an nRF9151 sip

9131

0x00009131

Device is an nRF9131 sip

SIPINFO.HWREVISION[n] (n=0..3)

Address offset: 0x144 + (n × 0x1)

SIP hardware revision, encoded in ASCII, for example B0A or B1A

Note: When treated as a c-string, content is not NULL-terminated.
Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0xFF 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

HWREVISION

SIPINFO.VARIANT[n] (n=0..3)

Address offset: 0x148 + (n × 0x1)

SIP VARIANT, encoded in ASCII, for example LACA. See Ordering information for details.

Note: When treated as a c-string, content is not NULL-terminated.
Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0xFF 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

VARIANT

VARIANT[0] contains the most significant character of the SIP VARIANT. VARIANT[3] contains the least significant character of the SIP VARIANT.

A

0x41

B

0x42

C

0x43

I

0x49

L

0x4C

S

0x53

INFO

Device info

INFO.DEVICEID[n] (n=0..1)

Address offset: 0x204 + (n × 0x4)

Device identifier

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

DEVICEID

64 bit unique device identifier

DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier.

INFO.RAM

Address offset: 0x218

RAM variant

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

RAM

RAM variant

K256

0x100

256 kByte RAM

Unspecified

0xFFFFFFFF

Unspecified

INFO.FLASH

Address offset: 0x21C

Flash variant

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

FLASH

Flash variant

K1024

0x400

1 MByte FLASH

INFO.CODEPAGESIZE

Address offset: 0x220

Code memory page size

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00001000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

CODEPAGESIZE

Code memory page size

K4096

0x1000

4 kByte

INFO.CODESIZE

Address offset: 0x224

Code memory size

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

CODESIZE

Code memory size in number of pages

Total code space is: CODEPAGESIZE * CODESIZE

P256

256

256 pages

INFO.DEVICETYPE

Address offset: 0x228

Device type

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

DEVICETYPE

Device type

Die

0x0000000

Device is an physical DIE

FPGA

0xFFFFFFFF

Device is an FPGA

TRIMCNF[n].ADDR (n=0..255)

Address offset: 0x300 + (n × 0x8)

Address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

Address

Address

TRIMCNF[n].DATA (n=0..255)

Address offset: 0x304 + (n × 0x8)

Data

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

Data

Data

TRNG90B

NIST800-90B RNG calibration data

TRNG90B.BYTES

Address offset: 0xC00

Amount of bytes for the required entropy bits

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

BYTES

Amount of bytes for the required entropy bits

TRNG90B.RCCUTOFF

Address offset: 0xC04

Repetition counter cutoff

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

RCCUTOFF

Repetition counter cutoff

TRNG90B.APCUTOFF

Address offset: 0xC08

Adaptive proportion cutoff

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

APCUTOFF

Adaptive proportion cutoff

TRNG90B.STARTUP

Address offset: 0xC0C

Amount of bytes for the startup tests

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

STARTUP

Amount of bytes for the startup tests

TRNG90B.ROSC1

Address offset: 0xC10

Sample count for ring oscillator configuration 1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

ROSC1

Sample count for ring oscillator configuration 1

TRNG90B.ROSC2

Address offset: 0xC14

Sample count for ring oscillator configuration 2

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

ROSC2

Sample count for ring oscillator configuration 2

TRNG90B.ROSC3

Address offset: 0xC18

Sample count for ring oscillator configuration 3

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

ROSC3

Sample count for ring oscillator configuration 3

TRNG90B.ROSC4

Address offset: 0xC1C

Sample count for ring oscillator configuration 4

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

ROSC4

Sample count for ring oscillator configuration 4