Configuration interface for trace and debug

Please refer to the Trace section for more information about how to configure the trace and debug interface.

Note: Although there are PSEL registers for the trace port, each function can only be mapped to a single pin due to pin speed requirements. Setting the PIN field to anything else will not have any effect. See Pin assignment chapter for more information

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA
TAD 0xE0080000 HF S NA No

Trace and debug control

Register overview

Register Offset TZ Description
TASKS_CLOCKSTART 0x000

Start all trace and debug clocks.
TASKS_CLOCKSTOP 0x004

Stop all trace and debug clocks.
ENABLE 0x500

Enable debug domain and aquire selected GPIOs
PSEL.TRACECLK 0x504

Pin configuration for TRACECLK
PSEL.TRACEDATA0 0x508

Pin configuration for TRACEDATA[0]
PSEL.TRACEDATA1 0x50C

Pin configuration for TRACEDATA[1]
PSEL.TRACEDATA2 0x510

Pin configuration for TRACEDATA[2]
PSEL.TRACEDATA3 0x514

Pin configuration for TRACEDATA[3]
TRACEPORTSPEED 0x518

Clocking options for the Trace Port debug interface

Reset behavior is the same as debug components

This register is retained.

TASKS_CLOCKSTART

Address offset: 0x000

Start all trace and debug clocks.

Note: The TASKS_CLOCKSTART task asserts the CTRL/STAT.CSYSPWRUPACK and CTRL/STAT.CDBGPWRUPACK (see Arm CoreSight SoC-400 Technical Reference Manual, revision r3p2).
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_CLOCKSTART

Start all trace and debug clocks.

Note: The TASKS_CLOCKSTART task asserts the CTRL/STAT.CSYSPWRUPACK and CTRL/STAT.CDBGPWRUPACK (see Arm CoreSight SoC-400 Technical Reference Manual, revision r3p2).

Trigger

1

Trigger task

TASKS_CLOCKSTOP

Address offset: 0x004

Stop all trace and debug clocks.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKS_CLOCKSTOP

Stop all trace and debug clocks.

Trigger

1

Trigger task

ENABLE

Address offset: 0x500

Enable debug domain and aquire selected GPIOs

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ENABLE

DISABLED

0

Disable debug domain and release selected GPIOs

ENABLED

1

Enable debug domain and aquire selected GPIOs

PSEL.TRACECLK

Address offset: 0x504

Pin configuration for TRACECLK

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

Pin number

Traceclk

21

TRACECLK pin

Note: Only this pin is valid
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.TRACEDATA0

Address offset: 0x508

Pin configuration for TRACEDATA[0]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

Pin number

Tracedata0

22

TRACEDATA0 pin

Note: Only this pin is valid
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.TRACEDATA1

Address offset: 0x50C

Pin configuration for TRACEDATA[1]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

Pin number

Tracedata1

23

TRACEDATA1 pin

Note: Only this pin is valid
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.TRACEDATA2

Address offset: 0x510

Pin configuration for TRACEDATA[2]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

Pin number

Tracedata2

24

TRACEDATA2 pin

Note: Only this pin is valid
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

PSEL.TRACEDATA3

Address offset: 0x514

Pin configuration for TRACEDATA[3]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PIN

Pin number

Tracedata3

25

TRACEDATA3 pin

Note: Only this pin is valid
B

RW

CONNECT

Connection

Disconnected

1

Disconnect

Connected

0

Connect

TRACEPORTSPEED (Retained)

Address offset: 0x518

Clocking options for the Trace Port debug interface

Reset behavior is the same as debug components

This register is retained.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TRACEPORTSPEED

Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock.

32MHz

0

Trace Port clock is:

32MHz

16MHz

1

Trace Port clock is:

16MHz

8MHz

2

Trace Port clock is:

8MHz

4MHz

3

Trace Port clock is:

4MHz